7630 datasheet(200/238 Pages) RENESAS

200 / 238 page

3-29

7630 Group User’s Manual

APPENDIX

3.5 List of registers

Fig. 3.5.15 Structure of Timer 2

Fig. 3.5.16 Structure of Timer 123 mode register

Timer 2

b7 b6 b5 b4 b3 b2 b1 b0

Function

At reset

Timer 2 (T2) [Address : 001716]

q Set “0016” to “FF16” as Timer 2 count value.

q The timer value is written to Timer 2 and latch at the same time

or to the latch only (Note).

q To get the actual Timer 2 value read out the Timer 2 register.

Note: Depinding on the Timer 2 write control bit (bit 2 of the Timer 123 mode register

[address: 001916] ).

Timer 123 mode register

b7 b6 b5 b4 b3 b2 b1 b0

Function

At reset

Name

Timer 123 mode register (T123M) [Address : 001916]

PWM output enable bit

0 : PWM output disabled

1 : PWM output enabled

Timer 2 write control bit

Timer 2 count source selection bit

Timer 3 count source selection bit

Pre-divider division ratio bits

0 : Latch and counter

1 : Latch only

0 : Timer 1 underflow

1 : Pre-divider output

0 : Timer 1 underflow

1 : Pre-divider output

b7 b6

0 0 :

φ divided by 1 (Note)

0 1 :

φ divided by 8 (Note)

1 0 :

φ divided by 32 (Note)

1 1 :

φ divided by 128 (Note)

Not used (“0” when read, don't write “1”.)

PWM polarity selection bit

0 : Start on “H” level output

1 : Start on “L” level output

Note: The internal system clock

φ is divided f(XIN) by 2 or by 8. The division ratio is decided by

the Internal system clock selection bit (bit 6 of the CPU mode register [address: 000016] ).

7630 Datasheet(PDF) 200 Page - Renesas Technology Corp

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