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HC210 Datasheet(PDF) 125 Page - Altera Corporation |
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HC210 Datasheet(HTML) 125 Page - Altera Corporation |
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125 / 228 page  Altera Corporation 5–33 September 2008 HardCopy II Utilities Menu HardCopy II Floorplan View The Quartus II software displays the preliminary timing closure floorplan and placement of your HardCopy II companion revision. This floorplan shows the preliminary placement and connectivity of all I/O pins, PLLs, memory blocks, HCell macros, and DSP HCell macros. Congestion mapping of routing connections can be viewed using the Layers Setting dialog box (in the View menu) settings. This is useful in analyzing densely packed areas of your floorplan that could be reducing the peak performance of your design. The HardCopy Design Center verifies final HCell macro timing and placement to guarantee timing closure is achieved. Figure 5–15 shows an example of the HC230F1020 device floorplan. Figure 5–15. HC230F1020 Device Floorplan In this small example design, the logic is placed near the bottom edge. You can see the placement of a DSP block constructed of HCell Macros, various logic HCell Macros, and an M4K memory block. A labeled close-up view of this region is shown in Figure 5–16. |
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