HC210 datasheet(140/228 Pages) ALTERA

140 / 228 page

6–12

Altera Corporation

September 2008

HardCopy Series Handbook, Volume 1

The key global variables for a HardCopy II project are listed in Table 6–4.

Table 6–4. Key HardCopy II Design Settings

Global Variable Name <name>

Value Description <value>

VERILOG_FILE

Verilog file name.

VHDL_FILE

VHDL file name.

AHDL_FILE

Altera HDL file name.

EDIF_FILE

EDIF file name.

BDF_FILE

Altera schematic file name.

FAMILY

Device family name, for example, Stratix II.

DEVICE

Prototype FPGA target device name.

TOP_LEVEL_ENTITY

Top-level design entity or module name.

DEVICE_TECHNOLOGY_MIGRATION_LIST

HardCopy II target device name.

COMPANION_REVISION

HardCopy II design revision name.

ENABLE_DRC_SETTINGS

Turn on the Design Assistant.

USE_TIMEQUEST_TIMING_ANALYZER

Set TimeQuest as the default timing analyzer <ON>.

SDC_FILE

File of TimeQuest constraints <constraint_file.sdc>.

You only need the following settings when using Classic Timing Analyzer. Using

Classic Timing Analyzer is not recommended.

REPORT_IO_PATHS_SEPARATELY

Creates a separate report panel for input and output min

and max timing results.

FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Timing constraints are checked for completeness (all clock

domains constraints and minimum and maximum

constraints are set for all I/O paths).

DO_COMBINED_ANALYSIS

Timing analysis are run for fast and slow operating

conditions and for best and worst-case timing analysis,

respectively.

IGNORE_CLOCK_SETTINGS

This must be turned off.

ENABLE_RECOVERY_REMOVAL_ANALYSIS

Verify recovery and removal times on asynchronous

control and reset signals.

ENABLE_CLOCK_LATENCY

Clock latency is included in timing analysis to asses

clock-insertion timing and clock skew.

HC210 Datasheet(PDF) 140 Page - Altera Corporation

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