78M6612-IMSLASHFSLASHP datasheet(32/111 Pages) TERIDIAN

32 / 111 page

78M6612 Data Sheet

DS_6612_001

Rev. 1.2

Special Function Registers for Interrupts

The following SFR registers control the interrupt functions:

• The interrupt enable Registers: IEN0, IEN1 and IEN2 (see Table 24, Table 25 and Table 26).

• The Timer/Counter control registers: The Timer/Counter control registers: TCON and T2CON

Table 27

(see

and Table 28).

• The interrupt request register: IRCON

Table 29

(see

• The interrupt priority registers: IP0 and IP1

Table 33

(see

and Table 34).

Interrupt Enable 0 Register (IEN0

Table 24: The

)

IEN0 Register

MSB

LSB

EAL

–

WDT

ES0

ET1

EX1

ET0

EX0

Bit

Symbol

Function

IEN0[7]

EAL

EAL=0 – disable all interrupts.

IEN0[6]

Not used for interrupt control.

WDT

–

IEN0[5]

IEN0[4]

ES0

ES0=0 – disable serial channel 0 interrupt.

IEN0[3]

ET1

ET1=0 – disable timer 1 overflow interrupt.

IEN0[2]

EX1

EX1=0 – disable external interrupt 1.

IEN0[1]

ET0

ET0=0 – disable timer 0 overflow interrupt.

IEN0[0]

EX0

EX0=0 – disable external interrupt 0.

Interrupt Enable 1 Register (IEN1

Table 25: The

)

IEN1

–

MSB

LSB

SWDT

EX6

EX5

EX4

EX3

–

EX2

Bit

Symbol

Function

–

IEN1[7]

IEN1[6]

Not used for interrupt control.

SWDT

IEN1[5]

EX6

EX6=0 – disable external interrupt 6.

IEN1[4]

EX5

EX5=0 – disable external interrupt 5.

IEN1[3]

EX4

EX4=0 – disable external interrupt 4.

IEN1[2]

EX3

EX3=0 – disable external interrupt 3.

IEN1[1]

EX2

EX2=0 – disable external interrupt 2.

–

IEN1[0]

78M6612-IM/F/P Datasheet(PDF) 32 Page - Teridian Semiconductor Corporation

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