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78M6612-IM/F/P Datasheet(PDF) 84 Page - Teridian Semiconductor Corporation |
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78M6612-IM/F/P Datasheet(HTML) 84 Page - Teridian Semiconductor Corporation |
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84 / 111 page ![]() 78M6612 Data Sheet DS_6612_001 84 Rev. 1.2 must be 12 (allowing for one settling cycle). The required configuration is FIR_LEN = 1 (three cycles per conversion) and MUX_DIV[1:0] = 01 (4 conversions per mux frame). During operation, the MPU is in charge of controlling the multiplexer cycles, for example by inserting an alternate multiplexer sequence at regular intervals using MUX_ALT. This enables temperature measurement. The polarity of chopping circuitry must be altered for each sample. It must also alternate for each alternate multiplexer reading. This is accomplished by maintaining CHOP_E = 00. 4.4.5 CE Calculations The CE performs the precision computations necessary to accurately measure energy. These computations include offset cancellation, products, product smoothing, product summation, frequency detection, VAR calculation, sag detection, peak detection, and voltage phase measurement. Refer to the applicable 78M6612 Firmware Description Document. 4.4.6 CE Status Since the CE_BUSY interrupt occurs at 2520.6 Hz, it is desirable to minimize the computation required in the interrupt handler of the MPU. The MPU can read the CE status word at every CE_BUSY interrupt. CE Address Name 0x70 Description CESTATUS See description of CE status word below. The CE Status Word is used for generating early warnings to the MPU. It contains sag warnings for VA as well as F0, the derived clock operating at the fundamental input frequency. CESTATUS provides information about the status of voltage and input AC signal frequency, which are useful for generating early power fail warnings, e.g. to initiate necessary data storage. CESTATUS represents the status flags for the preceding CE code pass (CE busy interrupt). Sag alarms are not remembered from one code pass to the next. The CE Status word is refreshed at every CE_BUSY interrupt. The significance of the bits in CESTATUS is shown in the table below: CESTATUS [bit] Name Description 31-29 Not Used These unused bits will always be zero. 28 F0 F0 is a square wave at the exact fundamental input frequency. 27 Reserved 26 SAG_B Normally zero. Becomes one when VB remains below SAG_THR for SAG_CNT samples. Will not return to zero until VB rises above SAG_THR. 25 SAG_A Normally zero. Becomes one when VA remains below SAG_THR for SAG_CNT samples. Will not return to zero until VA rises above SAG_THR. 24-0 Not Used These unused bits will always be zero. |
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