78M6612-IMSLASHFSLASHP datasheet(34/111 Pages) TERIDIAN

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78M6612 Data Sheet

DS_6612_001

Rev. 1.2

Interrupt Request Register (IRCON

Table 29: The

)

IRCON

–

MSB

LSB

–

EX6

IEX5

IEX4

IEX3

–

IEX2

Bit

Symbol

Function

–

IRCON[7]

–

IRCON[6]

IRCON[5]

External interrupt 6 edge flag.

IEX6

IRCON[4]

External interrupt 5 edge flag.

IEX5

IRCON[3]

External interrupt 4 edge flag.

IEX4

IRCON[2]

External interrupt 3 edge flag.

IEX3

IRCON[1]

External interrupt 2 edge flag.

IEX2

–

IRCON[0]

Only TF0 and TF1 (timer 0 and timer 1 overflow flag) will be automatically cleared by hardware

when the service routine is called (Signals T0ACK and T1ACK – port ISR – active high when

the service routine is called).

1.4.9.2 External Interrupts

The 78M6612 MPU allows seven external interrupts. These are connected as shown in Table 30. The

direction of interrupts 2 and 3 is programmable in the MPU. Interrupts 2 and 3 should be programmed

for falling sensitivity. The generic 8051 MPU literature states that interrupt 4 through 6 are defined as

rising edge sensitive. Thus, the hardware signals attached to interrupts 5 and 6 are inverted to achieve

the edge polarity shown in Table 30.

Table 30: External MPU Interrupts

External

Interrupt

Connection

Polarity

Flag

Reset

Digital I/O High Priority

see DIO_Rx

automatic

Digital I/O Low Priority

see DIO_Rx

automatic

FWCOL0, FWCOL1

falling

automatic

CE_BUSY

falling

automatic

PLL_OK (rising), PLL_OK (falling)

rising

automatic

EEPROM busy

falling

automatic

XFER_BUSY OR RTC_1SEC

falling

manual

FWCOLx interrupts occur when the CE collides with a Flash write attempt. See the Flash write

description in Section 1.5.5 for more detail.

SFR (special function register) enable bits must be set to permit any of these interrupts to occur.

Likewise, each interrupt has its own flag bit, which is set by the interrupt hardware, and reset by the MPU

interrupt handler. Note that XFER_BUSY, RTC_1SEC, FWCOL0, FWCOL1, PLLRISE, PLLFALL, have

their own enable and flag bits in addition to the interrupt 6, 4, and 2 enable and flag bits.

78M6612-IM/F/P Datasheet(PDF) 34 Page - Teridian Semiconductor Corporation

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