78M6612-IMSLASHFSLASHP datasheet(76/111 Pages) TERIDIAN

76 / 111 page

78M6612 Data Sheet

DS_6612_001

Rev. 1.2

4.3

I/O RAM Description – Alphabetical Order

Bits with a W (write) direction are written by the MPU into configuration RAM. Typically, they are initially

stored in Flash memory and copied to the configuration RAM by the MPU. Some of the more frequently

programmed bits are mapped to the MPU SFR memory space. The remaining bits are mapped to the

address range 0x2xxx. Bits with R (read) direction can be read by the MPU. Columns labeled “Rst” and

“Wk” describe the bit values upon reset and wake, respectively. No entry in one of these columns means

the bit is either read-only or is powered by the non-volatile supply and is not initialized. Write-only bits will

return zero when they are read.

Table 50: I/O RAM Map – Alphabetical Order

Name

Location

Rst

Dir

ADC_E

Description

2005[3]

R/W

Enables ADC and VREF. W hen disabled, removes bias

current.

BME

2020[6]

–

R/W

Battery Measure Enable. W hen set, a load current is

immediately applied to the battery and it is connected to

the ADC to be measured on Alternative Mux Cycles. See

MUX_ALT bit.

CE_E

2000[4]

R/W

CE enable.

CE_LCTN[4:0]

20A8[4:0]

R/W

CE program location. The starting address for the CE

program is 1024*CE_LCTN. CE_LCTN must be defined

before the CE is enabled.

CHOP_E[1:0]

2002[5:4]

R/W

Chop enable for the reference bandgap circuit. The value

of CHOP will change on the rising edge of MUXSYNC

according to the value in CHOP_E:

00-toggle

01-positive

10-reversed

11-toggle

CKOUT_E[1:0]

except at the mux sync edge at the end of SUMCYCLE.

2004[5,4]

R/W

CKTEST Enable. The default is 00.

00-SEG19.

01-CK_FIR (5 MHz Mission, 32 kHz Brownout).

10-Not allowed (reserved for production test).

11-Same as 10.

COMP_STAT[0]

2003[0]

–

The status of the power fail comparator for V1.

DIO_R1[2:0]

DIO_R2[2:0]

DIO_R3[2:0]*

DIO_R4[2:0]

DIO_R5[2:0]

DIO_R6[2:0]

DIO_R7[2:0]

DIO_R8[2:0]

DIO_R9[2:0]

DIO_R10[2:0]

DIO_R11[2:0]

2009[6:4]

200A[2:0]

200A[6:4]

200B[2:0]

200B[6:4]

200C[2:0]

200C[6:4]

200D[2:0]

200D[6:4]

200E[2:0]

200E[6:4]

R/W

Connects dedicated I/O pins DIO2 through DIO11 as well

as input pin DIO1 to internal resources. DIO_R3[2:0] is

only available in the 68-pin package. If more than one

input is connected to the same resource, the ‘MULTIPLE’

column below specifies how they are combined.

DIO_Rx

Resource

Multiple

000

NONE

–

001

Reserved

010

T0 (Timer0 clock or gate)

011

T1 (Timer1 clock or gate)

100

High priority IO interrupt (int0 rising)

101

Low priority IO interrupt (int1 rising)

110

High priority IO interrupt (int0

falling)

111

Low priority IO interrupt (int1 falling)

DIO_DIR0[7:1]*

SFRA2

[7:1]

R/W

Programs the direction of pins DIO7- DIO1. DIO3 is only

available on the 68-pin package.

1 indicates output. Ignored if the pin is not configured as

I/O. See DIO_PV and DIO_PW for special option for DIO6

and DIO7 outputs. See DIO_EEX for special option for

DIO4 and DIO5.

78M6612-IM/F/P Datasheet(PDF) 76 Page - Teridian Semiconductor Corporation

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