78M6612-IMSLASHFSLASHP datasheet(43/111 Pages) TERIDIAN

43 / 111 page

DS_6612_001

78M6612 Data Sheet

Rev. 1.2

1.5.7

Digital I/O

The device includes up to 18 pins (QFN 68 package) or 16 pins (LQFP 64 package) of general purpose

digital I/O. These pins are compatible with 5V inputs (no current-limiting resistors are needed). Some of

them are dedicated DIO (DIO3), some are dual-function that can alternatively be used as LCD drivers

(DIO4-11, 14-17, 19-21) and some share functions with the optical port (DIO1, DIO2). On reset or

power-up, all DIO pins are inputs until they are configured for the desired direction under MPU control.

The pins are configured by the DIO registers and by the five bits of the LCD_NUM register (located in I/O

RAM). Once declared as DIO, each pin can be configured independently as an input or output with the

DIO_DIRn bits. A 3-bit configuration word, DIO_Rx, can be used for certain pins, when configured as

DIO, to individually assign an internal resource such as an interrupt or a timer control. Table 38 lists the

direction registers and configurability associated with each group of DIO pins. Table 39 shows the con-

figuration for a DIO pin through its associated bit in its DIO_DIR register.

Tables showing the relationship between LCD_NUM and the available segment/DIO pins can be found in

the Applications section and in Section 4.3 I/O Description under LCD_NUM[4:0].

Table 38: Data/Direction Registers and Internal Resources for DIO Pin Groups

DIO

Pin no. (64 LQFP)

–

Pin no. (68 QFN)

–

Data Register

–

DIO1=P1

Direction Register

(SFR 0x90)

–

DIO_DIR1 (SFR 0x91)

Internal Resources

Configurable

–

DIO

Pin no. (64 LQFP)

–

Pin no. (68 QFN)

–

Data Register

–

DIO2=P2

Direction Register

(SFR 0xA0)

–

DIO_DIR2

Internal Resources

Configurable

(SFR 0xA1)

–

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