78M6612-IMSLASHFSLASHP datasheet(41/111 Pages) TERIDIAN

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DS_6612_001

78M6612 Data Sheet

Rev. 1.2

1.5.4

Temperature Sensor

The device includes an on-chip temperature sensor for determining the temperature of the bandgap

reference. The MPU may request an alternate multiplexer frame containing the temperature sensor

output by asserting MUX_ALT. The primary use of the temperature data is to determine the magnitude of

compensation required to offset the thermal drift in the system (see Section 3.3 Temperature

Compensation).

1.5.5

Physical Memory

Flash Memory: The 78M6612 includes 32 KB of on-chip Flash memory. The Flash memory primarily

contains MPU and CE program code. It also contains images of the CE DRAM, MPU RAM, and I/O

RAM. On power-up, before enabling the CE, the MPU copies these images to their respective locations.

Allocated Flash space for the CE program cannot exceed 1024 words (2 KB). The CE program must

begin on a 1 KB boundary of the Flash address. The CE_LCTN[4:0] word defines which 1 KB boundary

contains the CE code. Thus, the first CE instruction is located at 1024*CE_LCTN[4:0]. CE_LCTN must

be defined before the CE is enabled.

The Flash memory is segmented into 512 byte individually erasable pages.

The CE engine cannot access its program memory when Flash write occurs. Thus, the Flash write

procedure is to begin a sequence of Flash writes when CE_BUSY falls (CE_BUSY interrupt) and to make

sure there is sufficient time to complete the sequence before CE_BUSY rises again. The actual time for

the Flash write operation will depend on the exact number of cycles required by the CE program.

Typically (CE program is 512 instructions, mux frame is 13 CK32 cycles), there will be 200 µs of Flash

write time, enough for 4 bytes of Flash write. If the CE code is shorter, there will be even more time.

Two interrupts warn of collisions between the MPU firmware and the CE timing. If a Flash write is

attempted while the CE is busy, the Flash write will not execute and the FW_COL0 interrupt will be

issued. If a Flash write is still in progress when the CE would otherwise begin a code pass, the code

pass is skipped, the write is completed, and the FW_COL1 interrupt is issued.

The bit FLASH66Z (see Table 50) defines the speed for accessing Flash memory. To minimize supply

current draw, this bit should be set to 1.

Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper

sequence. These special pattern/sequence requirements prevent inadvertent erasure of the Flash

memory.

The mass erase sequence is:

Write 1 to the FLSH_MEEN bit (SFR address 0xB2[1].

Write pattern 0xAA to FLSH_ERASE (SFR address 0x94).

The mass erase cycle can only be initiated when the ICE port is enabled.

The page erase sequence is:

Write the page address to FLSH_PGADR (SFR address 0xB7[7:1].

Write pattern 0x55 to FLSH_ERASE (SFR address 0x94).

The MPU may write to the Flash memory. This is one of the non-volatile storage options available to the

user in addition to external EEPROM.

78M6612-IM/F/P Datasheet(PDF) 41 Page - Teridian Semiconductor Corporation

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