78M6612-IMSLASHFSLASHP datasheet(6/111 Pages) TERIDIAN

6 / 111 page

78M6612 Data Sheet

DS_6612_001

Rev. 1.2

Tables

Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles.......................................................9

Table 2: CE DRAM Locations for ADC Results ......................................................................................12

Table 3: Memory Map ............................................................................................................................17

Table 4: Stretch Memory Cycle Width ....................................................................................................18

Table 5: Internal Data Memory Map .......................................................................................................19

Table 6: Special Function Registers Locations .......................................................................................19

Table 7: Special Function Registers Reset Values .................................................................................20

Table 8: PSW Register ............................................................................................................................21

Table 9: Port Registers ..........................................................................................................................22

Table 10: Special Function Registers.....................................................................................................22

Table 11: Baud Rate Generation............................................................................................................24

Table 12: UART Modes..........................................................................................................................24

Table 13: The S0CON Register...............................................................................................................25

Table 14: The S1CON Register...............................................................................................................26

Table 15: The TCON Register ................................................................................................................27

Table 16: The TMOD Register................................................................................................................28

Table 17: Timers/Counters Mode Description.........................................................................................28

Table 18: Timer Modes ..........................................................................................................................28

Table 19: The PCON Register ................................................................................................................29

Table 20: The IEN0 Register ..................................................................................................................30

Table 21: The IEN1 Register ..................................................................................................................30

Table 22: The IP0 Register.....................................................................................................................30

Table 23: The WDTREL Register ............................................................................................................31

Table 24: The IEN0 Register ..................................................................................................................32

Table 25: The IEN1 Register ..................................................................................................................32

Table 26: The IEN2 Register ..................................................................................................................33

Table 27: The TCON Register ................................................................................................................33

Table 28: The T2CON Bit Functions .......................................................................................................33

Table 29: The IRCON Register ...............................................................................................................34

Table 30: External MPU Interrupts .........................................................................................................34

Table 31: Interrupt Enable and Flag Bits................................................................................................35

Table 32: Priority Level Groups ..............................................................................................................36

Table 33: The IP0 Register.....................................................................................................................37

Table 34: The IP1 Register.....................................................................................................................37

Table 35: Priority Levels.........................................................................................................................37

Table 36: Interrupt Polling Sequence.....................................................................................................37

Table 37: Interrupt Vectors ....................................................................................................................38

Table 38: Data/Direction Registers and Internal Resources for DIO Pin Groups .....................................43

Table 39: DIO_DIR Control Bit ...............................................................................................................44

Table 40: Selectable Controls using the DIO_DIR Bits ...........................................................................45

Table 41: EECTRL Status Bits................................................................................................................46

Table 42: EECTRL Bits for 3-Wire Interface ............................................................................................47

Table 43: TMUX[4:0] Selections .............................................................................................................50

Table 44: Available Circuit Functions .....................................................................................................54

Table 45: Frequency over Temperature..................................................................................................65

Table 46: LCD and DIO Pin Assignment by LCD_NUM for the QFN-68 Package...................................68

Table 47: LCD and DIO Pin Assignment by LCD_NUM for the LQFP-64 Package.................................69

Table 48: I/O RAM Map – In Numerical Order........................................................................................74

Table 49: SFR Map – In Numerical Order ..............................................................................................75

Table 50: I/O RAM Map – Alphabetical Order ........................................................................................76

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