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82G33 Datasheet(PDF) 364 Page - Intel Corporation

Part # 82G33
Description  Graphics and Memory Controller Hub
PDF  437 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82G33 Datasheet(HTML) 364 Page - Intel Corporation

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Functional Description
364
Datasheet
10.6.1.4
DDC (Display Data Channel)
DDC is a standard defined by VESA. Its purpose is to allow communication between
the host system and display. Both configuration and control information can be
exchanged allowing plug- and-play systems to be realized. Support for DDC 1 and 2 is
implemented. The GMCH uses the DDC_CLK and DDC_DATA signals to communicate
with the analog monitor. The GMCH generates these signals at 2.5 V. External pull-up
resistors and level shifting circuitry should be implemented on the board.
The GMCH implements a hardware GMBus controller that can be used to control these
signals allowing for transactions speeds up to 400 kHz.
10.6.2
Digital Display Interface
The GMCH has several options for driving digital displays. The GMCH contains two
SDVO ports that are multiplexed on the PEG interface. When an external PEG graphics
accelerator is not present, the GMCH can use the multiplexed SDVO ports to provide
extra digital display options. These additional digital display capabilities may be
provided through an ADD2/Media Expansion Card, which is designed to plug in to a
PCI Express connector.
10.6.2.1
Multiplexed Digital Display Channels – Intel® SDVOB and Intel®
SDVOC
The GMCH has the capability to support digital display devices through two SDVO
ports multiplexed with the PEG signals. When an external graphics accelerator is used
via the PEG port, these SDVO ports are not available.
The shared SDVO ports each support a pixel clock up to 200 MHz and can support a
variety of transmission devices.
SDVOCTRLDATA is an open-drain signal that will act as a strap during reset to tell the
GMCH whether the interface is a PCI Express interface or an SDVO interface. When
implementing SDVO, either via ADD2 cards or with a down device, a pull-up is placed
on this line to signal to the GMCH to run in SDVO mode and for proper GMBus
operation.
10.6.2.2
ADD2/Media Expansion Card (MEC)
When an Intel® 3 Series Express Chipset platform uses a PEG connector, the
multiplexed SDVO ports may be used via an ADD2 or MEC card. The ADD2 card will be
designed to fit a standard PCI Express (x16) connector.
10.6.2.3
TMDS Capabilities
The GMCH is compliant with DVI Specification 1.0. When combined with a DVI
compliant external device and connector, the GMCH has a high speed interface to a
digital display (e.g., flat panel or digital CRT). The GMCH can drive a flat panel up to
1920x1200 or a dCRT/HDTV up to 1400x1050. Flat Panel is a fixed resolution display.
The GMCH supports panel fitting in the transmitter, receiver, or an external device,
but has no native panel fitting capabilities. The GMCH will however, provide unscaled
mode where the display is centered on the panel.



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