ADV7180WBSTZ datasheet(63/120 Pages) AD

63 / 120 page

Data Sheet

ADV7180

Rev. G | Page 63 of 120

CGMS and WSS

The CGMS and WSS data packets convey the same type of

information for different video standards. WSS is for PAL and

CGMS is for NTSC; therefore, the CGMS and WSS readback

registers are shared. WSS is biphase coded; the VDP performs a

biphase decoding to produce the 14 raw WSS bits in the CGMS/

WSS readback I2C registers and to set the CGMS_WSS_AVL bit.

CGMS_WSS_CLEAR, CGMS/WSS Clear, Address 0x78[2],

User Sub Map, Write Only, Self-Clearing

Setting CGMS_WSS_CLEAR to 1 reinitializes the CGMS/WSS

readback registers.

CGMS_WSS_AVL, CGMS/WSS Available, Address 0x78[2],

User Sub Map, Read Only

When CGMS_WSS_AVL is 0, CGMS/WSS was not detected.

When CGMS_WSS_AVL is 1, CGMS/WSS was detected.

VDP_CGMS_WSS_DATA_0[3:0], Address 0x7D[3:0];

VDP_CGMS_WSS_DATA_1[7:0], Address 0x7E[7:0];

VDP_CGMS_WSS_DATA_2[7:0], Address 0x7F[7:0];

User Sub Map, Read Only

These bits hold the decoded CGMS or WSS data.

Refer to Figure 46 and Figure 47 for the I2C-to-WSS and I2C-to-

CGMS bit mapping.

ACTIVE

VIDEO

VDP_CGMS_WSS_

DATA_1[5:0]

VDP_CGMS_WSS_DATA_2

RUN-IN

SEQUENCE

START

CODE

11.0µs

38.4µs

42.5µs

Figure 46. WSS Waveform

VDP_CGMS_WSS_DATA_1

VDP_CGMS_WSS_

DATA_0[3:0]

VDP_CGMS_WSS_DATA_2

REF

+100 IRE

+70 IRE

0 IRE

–40 IRE

11.2µs

49.1µs ± 0.5µs

CRC SEQUENCE

2.235µs ± 20ns

Figure 47. CGMS Waveform

Table 81. CGMS Readback Registers1

Signal Name

Address (User Sub Map)

CGMS_WSS_DATA_0[3:0]

VDP_CGMS_WSS_DATA_0[3:0]

125

0x7D

CGMS_WSS_DATA_1[7:0]

VDP_CGMS_WSS_DATA_1[7:0]

126

0x7E

CGMS_WSS_DATA_2[7:0]

VDP_CGMS_WSS_DATA_2[7:0]

127

0x7F

1 These registers are readback registers; default value does not apply.

ADV7180WBSTZ Datasheet(PDF) 63 Page - Analog Devices

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