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ADV7180WBSTZ Datasheet(PDF) 14 Page - Analog Devices |
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ADV7180WBSTZ Datasheet(HTML) 14 Page - Analog Devices |
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14 / 120 page  ADV7180 Data Sheet Rev. G | Page 14 of 120 40-LEAD LFCSP PIN 1 INDICATOR 1 DVDDIO 2 SFL 3 DGND 4 DVDDIO 5 P7 6 P6 7 P5 8 P4 9 P3 10 P2 23 AIN1 24 AGND 25 VREFP 26 VREFN 27 AVDD 28 AGND 29 AIN2 30 AIN3 NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO GND. 22 TEST_0 21 AGND LFCSP TOP VIEW (Not to Scale) ADV7180 Figure 9. 40-Lead LFCSP Pin Configuration Table 10. 40-Lead LFCSP Pin Function Descriptions Pin No. Mnemonic Type Description 1, 4 DVDDIO P Digital I/O Supply Voltage (1.8 V to 3.3 V). 2 SFL O Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder. 3, 15, 35, 40 DGND G Ground for Digital Supply. 5 to 10, 16, 17 P7 to P2, P1, P0 O Video Pixel Output Port. 11 LLC O Line-Locked Output Clock for the Output Pixel Data. Nominally 27 MHz but varies up or down according to video line length. 12 XTAL1 O This pin should be connected to the 28.6363 MHz crystal or not connected if an external 1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the crystal must be a fundamental crystal. 13 XTAL I Input Pin for the 28.6363 MHz Crystal. This pin can be overdriven by an external 1.8 V, 28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal. 14, 36 DVDD P Digital Supply Voltage (1.8 V). 18 PWRDWN I A logic low on this pin places the ADV7180 into power-down mode. 19 ELPF I The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 55. 20 PVDD P PLL Supply Voltage (1.8 V). 21, 24, 28 AGND G Ground for Analog Supply. 22 TEST_0 I This pin must be tied to DGND. 23, 29, 30 AIN1 to AIN3 I Analog Video Input Channels. 25 VREFP O Internal Voltage Reference Output. See Figure 55 for recommended output circuitry. 26 VREFN O Internal Voltage Reference Output. See Figure 55 for recommended output circuitry. 27 AVDD P Analog Supply Voltage (1.8 V). 31 RESET I System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset the ADV7180 circuitry. 32 ALSB I This pin selects the I2C address for the ADV7180. For ALSB set to Logic 0, the address selected for a write is 0x40; for ALSB set to Logic 1, the address selected is 0x42. 33 SDATA I/O I2C Port Serial Data Input/Output Pin. 34 SCLK I I2C Port Serial Clock Input. The maximum clock rate is 400 kHz. 37 VS/FIELD O Vertical Synchronization Output Signal/Field Synchronization Output Signal. 38 INTRQ O Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video (see Table 108). 39 HS O Horizontal Synchronization Output Signal. EPAD (EP) The exposed pad must be connected to GND. |
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