ADV7180WBSTZ datasheet(65/120 Pages) AD

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Data Sheet

ADV7180

Rev. G | Page 65 of 120

VITC

VITC has a sequence of 10 syncs between each data byte. The

VDP strips these syncs from the data stream to output only the

data bytes. The VITC results are available in Register

VDP_VITC_DATA_0 to Register VDP_VITC_DATA_8

(Register 0x92 to Register 0x9A, user sub map).

The VITC has a CRC byte at the end; the syncs in between each

data byte are also used in this CRC calculation. Because the syncs

in between each data byte are not output, the CRC is calculated

internally. The calculated CRC is available for the user in the

VDP_VITC_CALC_CRC register (Resister 0x9B, user sub map).

When the VDP completes decoding the VITC line, the

VITC_DATA_x and VITC_CRC registers are updated and the

VITC_AVL bit is set.

VITC_CLEAR, VITC Clear, Address 0x78[6],

User Sub Map, Write Only, Self-Clearing

Setting VITC_CLEAR to 1 reinitializes the VITC readback

registers.

VITC_AVL, VITC Available, Address 0x78[6],

User Sub Map, Read Only

When VITC_AVL is 0, VITC data was not detected.

When VITC_AVL is 1, VITC data was detected.

VITC Readback Registers

See Figure 49 for the I2C-to-VITC bit mapping.

BIT 0, BIT 1

BIT 88, BIT 89

VITC WAVEFORM

Figure 49. VITC Waveform and Decoded Data Correlation

Table 83. VITC Readback Registers1

Signal Name

Address (User Sub Map)

VITC_DATA_0[7:0]

VDP_VITC_DATA_0[7:0] (VITC Bits[9:2])

146

0x92

VITC_DATA_1[7:0]

VDP_VITC_DATA_1[7:0] (VITC Bits[19:12])

147

0x93

VITC_DATA_2[7:0]

VDP_VITC_DATA_2[7:0] (VITC Bits[29:22])

148

0x94

VITC_DATA_3[7:0]

VDP_VITC_DATA_3[7:0] (VITC Bits[39:32])

149

0x95

VITC_DATA_4[7:0]

VDP_VITC_DATA_4[7:0] (VITC Bits[49:42])

150

0x96

VITC_DATA_5[7:0]

VDP_VITC_DATA_5[7:0] (VITC Bits[59:52])

151

0x97

VITC_DATA_6[7:0]

VDP_VITC_DATA_6[7:0] (VITC Bits[69:62])

152

0x98

VITC_DATA_7[7:0]

VDP_VITC_DATA_7[7:0] (VITC Bits[79:72])

153

0x99

VITC_DATA_8[7:0]

VDP_VITC_DATA_8[7:0] (VITC Bits[89:82])

154

0x9A

VITC_CRC[7:0]

VDP_VITC_CALC_CRC[7:0]

155

0x9B

These registers are readback registers; default value does not apply.

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