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ADV7180WBSTZ Datasheet(PDF) 17 Page - Analog Devices |
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ADV7180WBSTZ Datasheet(HTML) 17 Page - Analog Devices |
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17 / 120 page  Data Sheet ADV7180 Rev. G | Page 17 of 120 48-LEAD LQFP 48 47 46 45 44 43 42 41 40 39 38 37 35 AIN5 34 AIN4 33 AIN3 30 VFEFN 31 AVDD 32 AGND 36 AIN6 29 VREFP 28 AGND 27 AIN2 25 PVDD 26 AIN1 2 DVDDIO 3 SFL 4 DVDDIO 7 P7 6 GPO0 5 GPO1 1 DGND 8 P6 9 P5 10 P4 12 P2 11 P3 NC = NO CONNECT 13 14 15 16 17 18 19 20 21 22 23 24 PIN 1 ADV7180 LQFP TOP VIEW (Not to Scale) Figure 11. 48-Lead LQFP Pin Configuration Table 12. 48-Lead LQFP Pin Function Descriptions Pin No. Mnemonic Type Description 1, 13, 19, 43 DGND G Digital Ground. 2, 4 DVDDIO P Digital I/O Supply Voltage (1.8V to 3.3 V). 3 SFL O Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder. 5, 6, 41, 42 GPO0 to GPO3 O General-Purpose Outputs. These pins can be configured via I2C to allow control of external devices. 7 to 12, 20, 22 P7 to P2, P1, P0 O Video Pixel Output Port. See Table 100 for output configuration for 8-bit and 16-bit modes. 14 LLC O This is a line-locked output clock for the pixel data output by the ADV7180. It is nominally 27 MHz but varies up or down according to video line length. 15, 48 NC No Connect Pins. These pins are not connected internally. 16 XTAL1 O This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an external 1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the crystal must be a fundamental crystal. 17 XTAL I This is the input pin for the 28.6363 MHz crystal, or this pin can be overdriven by an external 1.8 V, 28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal. 18, 44 DVDD P Digital Supply Voltage (1.8 V). 21 PWRDWN I A logic low on this pin places the ADV7180 in power-down mode. 23, 28, 32 AGND G Analog Ground. 24 ELPF I The recommended external loop filter must be connected to the ELPF pin, as shown in Figure 57. 25 PVDD P PLL Supply Voltage (1.8 V). 26, 27, 33 to 36 AIN1 to AIN6 I Analog Video Input Channels. 29 VREFP O Internal Voltage Reference Output. See Figure 57 for recommended output circuitry. 30 VREFN O Internal Voltage Reference Output. See Figure 57 for recommended output circuitry. 31 AVDD P Analog Supply Voltage (1.8 V). 37 RESET I System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset the ADV7180 circuitry. 38 ALSB I This pin selects the I2C address for the ADV7180. For ALSB set to Logic 0, the address selected for a write is 0x40; for ALSB set to Logic 1, the address selected is 0x42. 39 SDATA I/O I2C Port Serial Data Input/Output Pin. 40 SCLK I I2C Port Serial Clock Input. The maximum clock rate is 400 kHz. 45 VS/FIELD O Vertical Synchronization Output Signal/Field Synchronization Output Signal. 46 INTRQ O Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video (see Table 108). 47 HS O Horizontal Synchronization Output Signal. |
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