ADV7180WBSTZ datasheet(23/120 Pages) AD

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Data Sheet

ADV7180

Rev. G | Page 23 of 120

Timing Signals Output Enable

TIM_OE, Address 0x04[3]

The TIM_OE bit should be regarded as an addition to the TOD bit.

Setting it high forces the output drivers for HS, VS, and FIELD into

the active state (that is, driving state) even if the TOD bit is set.

If TIM_OE is set to low, the HS, VS, and FIELD pins are three-

stated depending on the TOD bit. This functionality is beneficial if

the decoder is only used as a timing generator. This may be the

case if only the timing signals are extracted from an incoming

signal or if the part is in free-run mode, where a separate chip

can output a company logo, for example.

For more information on three-state control, see the Three-

State Output Drivers section and the Three-State LLC Driver

section.

Individual drive strength controls are provided via the

DR_STR_x bits.

When TIM_OE is 0 (default), HS, VS, and FIELD are three-

stated according to the TOD bit.

When TIM_OE is 1, HS, VS, and FIELD are forced active all

the time.

Drive Strength Selection (Data)

DR_STR[1:0], Address 0xF4[5:4]

For EMC and crosstalk reasons, it may be desirable to strengthen or

weaken the drive strength of the output drivers. The DR_STR[1:0]

bits affect the P[15:0] for the 64-lead device or P[7:0] for the

48-lead, 40-lead, and 32-lead devices output drivers.

For more information on three-state control, see the Drive

Strength Selection (Clock) and the Drive Strength Selection

(Sync) sections.

Table 16. DR_STR Function

DR_STR[1:0]

Description

Low drive strength (1×)

01 (default)

Medium low drive strength (2×)

Medium high drive strength (3×)

High drive strength (4×)

Drive Strength Selection (Clock)

DR_STR_C[1:0], Address 0xF4[3:2]

The DR_STR_C[1:0] bits can be used to select the strength of

the clock signal output driver (LLC pin). For more information,

see the Drive Strength Selection (Sync) and the Drive Strength

Selection (Data) sections.

Table 17. DR_STR_C Function

DR_STR_C[1:0]

Description

Low drive strength (1×)

01 (default)

Medium low drive strength (2×)

Medium high drive strength (3×)

High drive strength (4×)

Drive Strength Selection (Sync)

DR_STR_S[1:0], Address 0xF4[1:0]

The DR_STR_S[1:0] bits allow the user to select the strength of

the synchronization signals with which HS, VS, and FIELD are

driven. For more information, see the Drive Strength Selection

(Data) section.

Table 18. DR_STR_S Function

DR_STR_S[1:0]

Description

Low drive strength (1×)

01 (default)

Medium low drive strength (2×)

Medium high drive strength (3×)

High drive strength (4×)

Enable Subcarrier Frequency Lock Pin

EN_SFL_PIN, Address 0x04[1]

The EN_SFL_PIN bit enables the output of subcarrier lock

information (also known as genlock) from the ADV7180 core

to an encoder in a decoder/encoder back-to-back arrangement.

When EN_SFL_PIN is 0 (default), the subcarrier frequency lock

output is disabled.

When EN_SFL_PIN is 1, the subcarrier frequency lock information

is presented on the SFL pin.

Polarity LLC Pin

PCLK, Address 0x37[0]

The polarity of the clock that leaves the ADV7180 via the LLC

pin can be inverted using the PCLK bit.

Changing the polarity of the LLC clock output may be necessary to

meet the setup-and-hold time expectations of follow-on chips.

When PCLK is 0, the LLC output polarity is inverted.

When PCLK is 1 (default), the LLC output polarity is normal

(see the Timing Specifications section).

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