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ADV7180WBSTZ Datasheet(PDF) 81 Page - Analog Devices |
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ADV7180WBSTZ Datasheet(HTML) 81 Page - Analog Devices |
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81 / 120 page  Data Sheet ADV7180 Rev. G | Page 81 of 120 Table 106. Interrupt System Register Map Details1, 2 Address Register Name RW 7 6 5 4 3 2 1 0 Reset Value (Hex) Dec Hex 64 40 Interrupt Configuration 1 RW INTRQ_DUR_ SEL[1] INTRQ_DUR_ SEL[0] MV_INTRQ_ SEL[1] MV_INTRQ_ SEL[0] MPU_STIM_ INTRQ INTRQ_OP_ SEL[1] INTRQ_OP_SEL[0] 0001x000 10 66 42 Interrupt Status 1 R MV_PS_CS_Q SD_FR_CHNG_Q SD_UNLOCK_Q SD_LOCK_Q 67 43 Interrupt Clear 1 W MV_PS_CS_CLR SD_FR_CHNG_ CLR SD_UNLOCK_ CLR SD_LOCK_CLR x0000000 00 68 44 Interrupt Mask 1 RW MV_PS_CS_ MSKB SD_FR_CHNG_ MSKB SD_UNLOCK_ MSKB SD_LOCK_MSKB x0000000 00 69 45 Raw Status 1 R MPU_STIM_ INTRQ EVEN_FIELD CCAPD 70 46 Interrupt Status 2 R MPU_STIM_ INTRQ_Q SD_FIELD_ CHNGD_Q GEMD_Q CCAPD_Q 71 47 Interrupt Clear 2 W MPU_STIM_ INTRQ_CLR SD_FIELD_ CHNGD_CLR GEMD_CLR CCAPD_CLR 0xx00000 00 72 48 Interrupt Mask 2 RW MPU_STIM_ INTRQ_MSKB SD_FIELD_ CHNGD_MSKB GEMD_MSKB CCAPD_MSKB 0xx00000 00 73 49 Raw Status 2 R SCM_LOCK SD_H_LOCK SD_V_LOCK SD_OP_50Hz 74 4A Interrupt Status 3 R PAL_SW_LK_ CHNG_Q SCM_LOCK_ CHNG_Q SD_AD_CHNG_Q SD_H_LOCK_ CHNG_Q SD_V_LOCK_ CHNG_Q SD_OP_CHNG_Q 75 4B Interrupt Clear 3 W PAL_SW_LK_ CHNG_CLR SCM_LOCK_ CHNG_CLR SD_AD_CHNG_ CLR SD_H_LOCK_ CHNG_CLR SD_V_LOCK_ CHNG_CLR SD_OP_CHNG_ CLR xx000000 00 76 4C Interrupt Mask 3 RW PAL_SW_LK_ CHNG_MSKB SCM_LOCK_ CHNG_MSKB SD_AD_CHNG_ MSKB SD_H_LOCK_ CHNG_MSKB SD_V_LOCK_ CHNG_MSKB SD_OP_CHNG_ MSKB xx000000 00 78 4E Interrupt Status 4 R VDP_VITC_Q VDP_GS_VPS_ PDC_UTC_ CHNG_Q VDP_CGMS_ WSS_CHNGD_Q VDP_CCAPD_Q 79 4F Interrupt Clear 4 W VDP_VITC_CLR VDP_GS_VPS_ PDC_UTC_ CHNG_CLR VDP_CGMS_ WSS_CHNGD_ CLR VDP_CCAPD_CLR 00x0x0x0 00 80 50 Interrupt Mask 4 RW VDP_VITC_MSKB VDP_GS_VPS_ PDC_UTC_ CHNG_MSKB VDP_CGMS_ WSS_CHNGD_ MSKB VDP_CCAPD_ MSKB 00x0x0x0 00 96 60 VDP_Config_1 RW WST_PKT_ DECODE_ DISABLE VDP_TTXT_ TYPE_MAN_ ENABLE VDP_TTXT_ TYPE_MAN[1] VDP_TTXT_ TYPE_MAN[0] 10001000 88 97 61 VDP_Config_2 RW AUTO_DETECT_ GS_TYPE 0001xx00 10 98 62 VDP_ADF_Config_1 RW ADF_ENABLE ADF_MODE[1] ADF_MODE[0] ADF_DID[4] ADF_DID[3] ADF_DID[2] ADF_DID[1] ADF_DID[0] 00010101 15 99 63 VDP_ADF_Config_2 RW DUPLICATE_ADF ADF_SDID[5] ADF_SDID[4] ADF_SDID[3] ADF_SDID[2] ADF_SDID[1] ADF_SDID[0] 0x101010 2A 100 64 VDP_LINE_00E RW MAN_LINE_PGM VBI_DATA_ P318[3] VBI_DATA_ P318[2] VBI_DATA_ P318[1] VBI_DATA_ P318[0] 0xxx0000 00 101 65 VDP_LINE_00F RW VBI_DATA_ P6_N23[3] VBI_DATA_ P6_N23[2] VBI_DATA_ P6_N23[1] VBI_DATA_ P6_N23[0] VBI_DATA_ P319_N286[3] VBI_DATA_ P319_N286[2] VBI_DATA_ P319_N286[1] VBI_DATA_ P319_N286[0] 00000000 00 102 66 VDP_LINE_010 RW VBI_DATA_ P7_N24[3] VBI_DATA_ P7_N24[2] VBI_DATA_ P7_N24[1] VBI_DATA_ P7_N24[0] VBI_DATA_ P320_N287[3] VBI_DATA_ P320_N287[2] VBI_DATA_ P320_N287[1] VBI_DATA_ P320_N287[0] 00000000 00 103 67 VDP_LINE_011 RW VBI_DATA_ P8_N25[3] VBI_DATA_ P8_N25[2] VBI_DATA_ P8_N25[1] VBI_DATA_ P8_N25[0] VBI_DATA_ P321_N288[3] VBI_DATA_ P321_N288[2] VBI_DATA_ P321_N288[1] VBI_DATA_ P321_N288[0] 00000000 00 104 68 VDP_LINE_012 RW VBI_DATA_ P9[3] VBI_DATA_ P9[2] VBI_DATA_ P9[1] VBI_DATA_ P9[0] VBI_DATA_ P322[3] VBI_DATA_ P322[2] VBI_DATA_ P322[1] VBI_DATA_ P322[0] 00000000 00 105 69 VDP_LINE_013 RW VBI_DATA_ P10[3] VBI_DATA_ P10[2] VBI_DATA_ P10[1] VBI_DATA_ P10[0] VBI_DATA_ P323[3] VBI_DATA_ P323[2] VBI_DATA_ P323[1] VBI_DATA_ P323[0] 00000000 00 106 6A VDP_LINE_014 RW VBI_DATA_ P11[3] VBI_DATA_ P11[2] VBI_DATA_ P11[1] VBI_DATA_ P11[0] VBI_DATA_ P324_N272[3] VBI_DATA_ P324_N272[2] VBI_DATA_ P324_N272[1] VBI_DATA_ P324_N272[0] 00000000 00 107 6B VDP_LINE_015 RW VBI_DATA_ P12_N10[3] VBI_DATA_ P12_N10[2] VBI_DATA_ P12_N10[1] VBI_DATA_ P12_N10[0] VBI_DATA_ P325_N273[3] VBI_DATA_ P325_N273[2] VBI_DATA_ P325_N273[1] VBI_DATA_ P325_N273[0] 00000000 00 108 6C VDP_LINE_016 RW VBI_DATA_ P13_N11[3] VBI_DATA_ P13_N11[2] VBI_DATA_ P13_N11[1] VBI_DATA_ P13_N11[0] VBI_DATA_ P326_N274[3] VBI_DATA_ P326_N274[2] VBI_DATA_ P326_N274[1] VBI_DATA_ P326_N274[0] 00000000 00 109 6D VDP_LINE_017 RW VBI_DATA_ P14_N12[3] VBI_DATA_ P14_N12[2] VBI_DATA_ P14_N12[1] VBI_DATA_ P14_N12[0] VBI_DATA_ P327_N275[3] VBI_DATA_ P327_N275[2] VBI_DATA_ P327_N275[1] VBI_DATA_ P327_N275[0] 00000000 00 110 6E VDP_LINE_018 RW VBI_DATA_ P15_N13[3] VBI_DATA_ P15_N13[2] VBI_DATA_ P15_N13[1] VBI_DATA_ P15_N13[0] VBI_DATA_ P328_N276[3] VBI_DATA_ P328_N276[2] VBI_DATA_ P328_N276[1] VBI_DATA_ P328_N276[0] 00000000 00 111 6F VDP_LINE_019 RW VBI_DATA_ P16_N14[3] VBI_DATA_ P16_N14[2] VBI_DATA_ P16_N14[1] VBI_DATA_ P16_N14[0] VBI_DATA_ P329_N277[3] VBI_DATA_ P329_N277[2] VBI_DATA_ P329_N277[1] VBI_DATA_ P329_N277[0] 00000000 00 112 70 VDP_LINE_01A RW VBI_DATA_ P17_N15[3] VBI_DATA_ P17_N15[2] VBI_DATA_ P17_N15[1] VBI_DATA_ P17_N15[0] VBI_DATA_ P330_N278[3] VBI_DATA_ P330_N278[2] VBI_DATA_ P330_N278[1] VBI_DATA_ P330_N278[0] 00000000 00 113 71 VDP_LINE_01B RW VBI_DATA_ P18_N16[3] VBI_DATA_ P18_N16[2] VBI_DATA_ P18_N16[1] VBI_DATA_ P18_N16[0] VBI_DATA_ P331_N279[3] VBI_DATA_ P331_N279[2] VBI_DATA_ P331_N279[1] VBI_DATA_ P331_N279[0] 00000000 00 114 72 VDP_LINE_01C RW VBI_DATA_ P19_N17[3] VBI_DATA_ P19_N17[2] VBI_DATA_ P19_N17[1] VBI_DATA_ P19_N17[0] VBI_DATA_ P332_N280[3] VBI_DATA_ P332_N280[2] VBI_DATA_ P332_N280[1] VBI_DATA_ P332_N280[0] 00000000 00 115 73 VDP_LINE_01D RW VBI_DATA_ P20_N18[3] VBI_DATA_ P20_N18[2] VBI_DATA_ P20_N18[1] VBI_DATA_ P20_N18[0] VBI_DATA_ P333_N281[3] VBI_DATA_ P333_N281[2] VBI_DATA_ P333_N281[1] VBI_DATA_ P333_N281[0] 00000000 00 116 74 VDP_LINE_01E RW VBI_DATA_ P21_N19[3] VBI_DATA_ P21_N19[2] VBI_DATA_ P21_N19[1] VBI_DATA_ P21_N19[0] VBI_DATA_ P334_N282[3] VBI_DATA_ P334_N282[2] VBI_DATA_ P334_N282[1] VBI_DATA_ P334_N282[0] 00000000 00 117 75 VDP_LINE_01F RW VBI_DATA_ P22_N20[3] VBI_DATA_ P22_N20[2] VBI_DATA_ P22_N20[1] VBI_DATA_ P22_N20[0] VBI_DATA_ P335_N283[3] VBI_DATA_ P335_N283[2] VBI_DATA_ P335_N283[1] VBI_DATA_ P335_N283[0] 00000000 00 |
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