ADV7180WBSTZ datasheet(28/120 Pages) AD

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ADV7180

Data Sheet

Rev. G | Page 28 of 120

SRLS, Select Raw Lock Signal, Address 0x51[6]

Using the SRLS bit, the user can choose between two sources for

determining the lock status (per Bits[1:0] in the Status 1 register).

See Figure 19.

•

The TIME_WIN signal is based on a line-to-line evaluation

of the horizontal synchronization pulse of the incoming

video. It reacts quite quickly.

•

The FREE_RUN signal evaluates the properties of the

incoming video over several fields, taking vertical

synchronization information into account.

Setting SRLS to 0 (default) selects the FREE_RUN signal.

Setting SRLS to 1 selects the TIME_WIN signal.

FSCLE, fSC Lock Enable, Address 0x51[7]

The FSCLE bit allows the user to choose whether the status of

the color subcarrier loop is taken into account when the overall

lock status is determined and presented via Bits[1:0] in the

Status 1 register. This bit must be set to 0 when operating the

ADV7180 in YPrPb component mode to generate a reliable

HLOCK status bit.

When FSCLE is set to 0 (default), only the overall lock status is

dependent on horizontal sync lock.

When FSCLE is set to 1, the overall lock status is dependent on

horizontal sync lock and fSC lock.

CIL[2:0], Count Into Lock, Address 0x51[2:0]

CIL[2:0] determines the number of consecutive lines for which

the lock condition must be true before the system switches into

the locked state and reports this via Status 1[1:0]. The bit counts

the value in lines of video.

Table 25. CIL Function

CIL[2:0]

Number of Video Lines

000

001

010

011

100 (default)

100

101

500

110

1000

111

100,000

COL[2:0], Count Out of Lock, Address 0x51[5:3]

COL[2:0] determines the number of consecutive lines for which

the out-of-lock condition must be true before the system switches

into the unlocked state and reports this via Status 1[1:0]. It counts

the value in lines of video.

Table 26. COL Function

COL[2:0]

Number of Video Lines

000

001

010

011

100 (default)

100

101

500

110

1000

111

100,000

COLOR CONTROLS

These registers allow the user to control picture appearance,

including control of the active data in the event of video being

lost. These controls are independent of any other controls. For

instance, brightness control is independent of picture clamping,

although both controls affect the dc level of the signal.

CON[7:0], Contrast Adjust, Address 0x08[7:0]

This register allows the user to control contrast adjustment of

the picture.

Table 27. CON Function

CON[7:0]

Description

0x80 (default)

Gain on luma channel = 1

0x00

Gain on luma channel = 0

0xFF

Gain on luma channel = 2

SD_SAT_Cb[7:0], SD Saturation Cb Channel,

Address 0xE3[7:0]

This register allows the user to control the gain of the Cb channel

only, which in turn adjusts the saturation of the picture.

Table 28. SD_SAT_Cb Function

SD_SAT_Cb[7:0]

Description

0x80 (default)

Gain on Cb channel = 0 dB

0x00

Gain on Cb channel = −42 dB

0xFF

Gain on Cb channel = +6 dB

SD_SAT_Cr[7:0], SD Saturation Cr Channel,

Address 0xE4[7:0]

This register allows the user to control the gain of the Cr channel

only, which in turn adjusts the saturation of the picture.

Table 29. SD_SAT_Cr Function

SD_SAT_Cr[7:0]

Description

0x80 (default)

Gain on Cr channel = 0 dB

0x00

Gain on Cr channel = −42 dB

0xFF

Gain on Cr channel = +6 dB

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