ADV7180WBSTZ datasheet(13/120 Pages) AD

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Data Sheet

ADV7180

Rev. G | Page 13 of 120

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

32-LEAD LFCSP

NOTES

1. THE EXPOSEDPAD MUST BE CONNECTEDTO GND.

DGND

DVDDIO

SFL

ELPF

PVDD

AIN1

VREFP

VREFN

AVDD

AIN2

AIN3

PIN1

INDICATOR

ADV7180

LFCSP

TOP VIEW

(Not to Scale)

Figure 8. 32-Lead LFCSP Pin Configuration

Table 9. 32-Lead LFCSP Pin Function Descriptions

Pin No.

Mnemonic

Type

Description

Horizontal Synchronization Output Signal.

2, 29

DGND

Ground for Digital Supply.

DVDDIO

Digital I/O Supply Voltage (1.8 V to 3.3 V).

SFL

Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the

subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder.

5 to 10, 15, 16

P7 to P2, P1, P0

Video Pixel Output Port.

LLC

Line-Locked Output Clock for the Output Pixel Data. Nominally 27 MHz but varies up or

down according to video line length.

XTAL1

This pin should be connected to the 28.6363 MHz crystal or not connected if an external

1.8 V,28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the

crystal must be a fundamental crystal.

XTAL

Input Pin for the 28.6363 MHz Crystal. This pin can be overdriven by an external 1.8 V,

28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.

14, 30

DVDD

Digital Supply Voltage (1.8 V).

ELPF

The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 58.

PVDD

PLL Supply Voltage (1.8 V).

19, 23, 24

AIN1 to AIN3

Analog Video Input Channels.

VREFP

Internal Voltage Reference Output. See Figure 58 for recommended output circuitry.

VREFN

Internal Voltage Reference Output. See Figure 58 for recommended output circuitry.

AVDD

Analog Supply Voltage (1.8 V).

RESET

System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to

reset the ADV7180 circuitry.

ALSB

This pin selects the I2C address for the ADV7180. For ALSB set to Logic 0, the address selected

for a write is 0x40; for ALSB set to Logic 1, the address selected is 0x42.

SDATA

I/O

I2C Port Serial Data Input/Output Pin.

SCLK

I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.

VS/FIELD

Vertical Synchronization Output Signal/Field Synchronization Output Signal.

INTRQ

Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video

(see Table 108).

EPAD (EP)

The exposed pad must be connected to GND.

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