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ADV7180WBSTZ Datasheet(PDF) 94 Page - Analog Devices |
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ADV7180WBSTZ Datasheet(HTML) 94 Page - Analog Devices |
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94 / 120 page  ADV7180 Data Sheet Rev. G | Page 94 of 120 Subaddress Register Bit Description Bits (Shading Indicates Default State) Comments Notes 7 6 5 4 3 2 1 0 0x59 General- purpose outputs GPO[3:0]; LQFP only 0 Outputs 0 to GPO0 GPO_ENABLE must be set to 1 for these bits to take effect 1 Outputs 1 to GPO0 0 Outputs 0 to GPO1 1 Outputs 1 to GPO1 0 Outputs 0 to GPO2 1 Outputs 1 to GPO2 0 Outputs 0 to GPO3 1 Outputs 1 to GPO3 GPO_ENABLE 0 GPO[3:0] three-stated 1 GPO[3:0] enabled Reserved 0 0 0 0x8F Free-Run Line Length 1 Reserved 0 0 0 0 Set to default LLC_PAD_SEL[2:0]; enables manual selection of the clock for the LLC pin 0 0 0 LLC (nominal 27 MHz) selected out on LLC pin 1 0 1 LLC (nominal 13.5 MHz) selected out on LLC pin For 16-bit 4:2:2 out, OF_SEL[3:0] = 0010 Reserved 0 Set to default 0x99 CCAP1 (read only) CCAP1[7:0]; closed caption data register x x x x x x x x CCAP1[7] contains parity bit for Byte 0 0x9A CCAP2 (read only) CCAP2[7:0]; closed caption data register x x x x x x x x CCAP2[7] contains parity bit for Byte 0 0x9B Letterbox 1 (read only) LB_LCT[7:0]; letterbox data register x x x x x x x x Reports the number of black lines detected at the top of active video This feature examines the active video at the start and end of each field; it enables format detection even if the video is not accompanied by a CGMS or WSS sequence 0x9C Letterbox 2 (read only) LB_LCM[7:0]; letterbox data register x x x x x x x x Reports the number of black lines detected in the bottom half of active video if subtitles are detected 0x9D Letterbox 3 (read only) LB_LCB[7:0]; letterbox data register x x x x x x x x Reports the number of black lines detected at the bottom of active video 0xB2 CRC enable (write only) Reserved 0 0 Set as default CRC_ENABLE; enable CRC checksum decoded from FMS packet to validate CGMSD 0 Turn off CRC check 1 CGMSD goes high with valid checksum Reserved 0 0 0 1 1 Set as default 0xC3 ADC Switch 1 MUX0[2:0]; manual muxing control for MUX0; this setting controls which input is routed to the ADC for processing LQFP LFCSP MAN_MUX_EN = 1 0 0 0 No connect No connect 0 0 1 AIN1 AIN1 0 1 0 AIN2 No connect 0 1 1 AIN3 No connect 1 0 0 AIN4 AIN2 1 0 1 AIN5 AIN3 1 1 0 AIN6 No connect 1 1 1 No connect No connect Reserved 0 MUX1[2:0]; manual muxing control for MUX1; this setting controls which input is routed to the ADC for processing LQFP LFCSP MAN_MUX_EN = 1 0 0 0 No connect No connect 0 0 1 No connect No connect 0 1 0 No connect No connect 0 1 1 AIN3 No connect 1 0 0 AIN4 AIN2 1 0 1 AIN5 AIN3 1 1 0 AIN6 No connect 1 1 1 No connect No connect Reserved 0 |
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