MT312CSLASHCG datasheet(48/90 Pages) ZARLINK

48 / 90 page

MT312 Forward Error Correction

B0:

BER tog High = BER toggle. This bit enables the audio signal output on the STATUS pin it indicates

BER during dish alignment, see 12, section 1.4.1.2. The frequency of the signal is controlled by

VIT MAXERR register (94), see 70.

7.1.3 FEC Set Up. Register 97 (R/W)

B7:

When MANUAL MOCLK (register 96 bit 7) is Low then:

DIS SR

High = Disable use of Symbol Rate for MOCLK generation.

Low = Use Symbol Rate for MOCLK generation.

When MANUAL MOCLK (register 96 bit 7) is High then:

DIS SR

High = Use external MICLK (pin 14) signal for MOCLK.

Low = Manually set MOCLK period from MOCLK RATIO (reg. 33).

B6:

ENCLKO

High = Enable clock out for test purposes.

B5:

DIS DS

High = Disable de-scrambler.

B4:

DIS RS

High = Disable Reed Solomon decoder.

B3:

DIS VIT

High = Disable Viterbi (Viterbi by pass mode)

B2:

EN PRS

High = Enable programmed synchronisation byte in register 98.

B1-0:DS LK[1:0] + 2 =Number of bytes for de-scrambler to lose lock. The default register value of 3 is

equivalent to 5 bad sync words.

7.2 Forward Error Correction Read Registers

7.2.1 FEC Interrupt. Register 3 (R)

B7:

High = DiSEqC™

B6:

High = Byte Align lock lost

B5:

High = Byte Align lockimportant indicator.

B4:

High = Viterbi lock lost

B3:

High = Viterbi lock

NAME

ADR

Def

hex

FEC SETUP

DIS SR

ENCL

DIS

VIT

PRS

DS LK[1:0]

R/W

NAME

ADR

Def

hex

FEC INT

FEC INT[7:0] Interrupt FEC

MT312C/CG Datasheet(PDF) 48 Page - Zarlink Semiconductor Inc

MT312C/CG Datasheet(HTML) 48 Page - Zarlink Semiconductor Inc

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