MT312CSLASHCG datasheet(34/90 Pages) ZARLINK

34 / 90 page

MT312 DiSEqC Control

B1:

End of message interrupt (reset on read).

Bit B1 indicates a new message has been received. The end of a message is identiﬁed by a silent

period of about 6 ms following a byte. The end-of-message interrupt bit makes it easier for the host

processor to read DiSEqC™ data from MT312. Instead of reading a byte at a time, it can read the

message as a whole.

It is important to note that MT312 does not stop accepting bytes after setting end-of-message

interrupt. It will receive new messages, if any, whilst the current message is being read by the host.

Since 2-wire bus read rate is higher than the byte receive rate, there is no reason for FIFO buffer

overﬂow. After every received message there will be an interrupt.

B0:

End of byte interrupt (reset on read).

Bit B0 is set when a new byte is received. The host may wish to ignore byte interrupts and opt to read

received messages, as described below.

It is important to note that MT312 does not stop accepting bytes after setting end-of-message

interrupt. It will receive new messages, if any, whilst the current message is being read by the host.

Since 2-wire bus read rate is higher than the byte receive rate, there is no reason for FIFO buffer

overﬂow.

After every received message there will be an interrupt.

5.3.2 DiSEqC™M 2 Status Indicators. Register 119 (R)

B7-5:

DISEQC2 Finite State Machine State. This is primarily for debugging the device.

B4-0:

Silent period since last received bit, in multiples of 16 ms.

Bits B4-0 is reset to zero when a bit is received. When this 5-bit number reaches 176, the interrupt bit

B3 of DISEQC2 INT register is set. This is saturated to 31. Hence if the total period exceeds 496

ms this counter will continue to indicate 31.

5.3.3 DiSEqC™ 2 FIFO. Register 120 (R)

Odd byte read of register 120:

Even byte read of register 120:

This FIFO contains data bytes and parity bits collected. This can hold a maximum of 8 data bytes, 8 parity bits

and 8 parity error bits. The parity error bit is deﬁned as the inverse of the exclusive-OR combination (or

modulo-2 addition) of all 9 bits (8 data and 1 parity). This bit will be zero when there is no parity error.

NAME

ADR

Def

hex

DISEQC2 STAT

119

DISEQC2 STATUS[7:0]

NAME

ADR

Def

hex

DISEQC2 FIFO

120

DISEQC2 FIFO[7:0]

MT312C/CG Datasheet(PDF) 34 Page - Zarlink Semiconductor Inc

MT312C/CG Datasheet(HTML) 34 Page - Zarlink Semiconductor Inc

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