MT312CSLASHCG datasheet(38/90 Pages) ZARLINK

38 / 90 page

MT312 QPSK Demodulator

6.1.2 Viterbi mode. Register 25 (R/W)

B7:

AUT IQ

Automatic IQ phaseHigh = Search for correct IQ phase.

Low = Use IQ phase setting in V IQ SP.

When this bit is set high, the Viterbi decoder will start with the IQ phase deﬁned in V IQ SP and the

code rate deﬁned in VIT MODE[5:0], to establish the correct IQ phase of the incoming signal. When

this is established, the V IQ SP bit will be set to that phase indication so that it can be read by

software for subsequent re-tuning to the same channel.

B6:

V IQ SP

Swap I and Q inputs to the Viterbi decoder to overcome

spectral inversion caused by the transmitter.

High = I-Q swap

Low = No I-Q swap

If the transmitted signal is known to be spectrally inverted then set this bit to 1. If the spectral inversion

status of the transmitted signal is not known, then after QPSK CT lock, try to achieve FEC lock with

this bit ﬁrst at zero and then at one.

When AUT IQ is set high, this bit will indicate the IQ phase following successful channel acquisition.

In manual mode, when AUT IQ is set low, software is required to determine the spectrum phase and

control this bit externally.

B5:

CR 7/8

High = Viterbi code rate 7/8.

B4:

CR 6/7

High = Viterbi code rate 6/7.

B3:

CR 5/6

High = Viterbi code rate 5/6.

B2:

CR 3/4

High = Viterbi code rate 3/4.

B1:

CR 2/3

High = Viterbi code rate 2/3.

B0:

CR 1/2

High = Viterbi code rate 1/2.

NAME

ADR

Def

hex

VIT MODE

AUT IQ

V IQ

7/8

6/7

5/6

3/4

2/3

1/2

R/W

MT312C/CG Datasheet(PDF) 38 Page - Zarlink Semiconductor Inc

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