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MT312C/CG Datasheet(PDF) 73 Page - Zarlink Semiconductor Inc

Part # MT312C/CG
Description  Satellite Channel Decoder
PDF  90 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

MT312C/CG Datasheet(HTML) 73 Page - Zarlink Semiconductor Inc

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Secondary Registers for Test and De-Bugging
MT312
73
10.2.51 QPSK Test State. Register 106 (R/W)
QPSK TEST ST (106)
Default value
0 dec.
00 hex.
QPSK TEST ST[7:0]
For factory test purposes only.
10.2.52 Test Mode. Register 125 (R/W)
TEST MODE (125)
Default value
0 dec.
00 hex.
TEST MODE[7:0]:
This register is for testing purposes only.
10.3 Read only Secondary Register Map
Writing to these registers will have no effect.
10.4 Secondary Registers for Test and De-Bugging Read Register
10.4.1 Test Read. Register 107 (R)
TEST R (107) Default value0 dec.00 hex.
TEST R[7:0]For test purposes only.
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
Def
hex
TEST R
107
TEST R[7:0] Test Read, for test purposes only.
R
00



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