MT312CSLASHCG datasheet(65/90 Pages) ZARLINK

65 / 90 page

Secondary Registers for Test and De-Bugging

MT312

10.2.15 Carrier Synchronisation Sweep Rate 3. Register 55 (R/W)

CS SW

Default value

112 dec.

70 hex.

RATE 3 (55)

CS SW

Carrier Synchronisation sweep rate 3.

RATE 3[7:0]

10.2.16 Carrier Synchronisation Sweep Rate 4. Register 56 (R/W)

CS SW

Default value

144 dec.

90 hex.

RATE 4 (56)

CS SW

Carrier Synchronisation sweep rate 4.

RATE 4[7:0]

10.2.17 Carrier Synchronisation Sweep Limit. Register 57 (R/W)

CS SW

Default value

124 dec.

7C hex.

LIM (57)

CS SW

Carrier Synchronisation sweep limit.

LIM[7:0]

10.2.18 Timing Synchronisation Coefﬁcients. Registers 58 - 60 (R/W)

B23-12:

TS KPROPE[11:0]

Timing Synchronisation Proportional path coefﬁcients.

B11-0:

TS KINTE [11:0]

Timing Synchronisation Integration path coefﬁcients.

10.2.19 Carrier Synchronisation Proportional Part Coefﬁcients. Registers 61 - 62 (R/W)

B15:

NONSNR

High = Non SNR sweep.

B14-10:

CS KP2[4:0]

Carrier proportional tracking coefﬁcients.

B9-5:

CS KP14:0]

Carrier proportional transition coefﬁcients.

B4-0:

CS KP04:0]

Carrier proportional acquire coefﬁcients.

NAME

ADR

Def

hex

TS LPK H

TS KPROPE[11:4]

R/W

TS LPK M

TS KPROPE93:0]

TS KINTE[11:8]

R/W

TS LPK L

TS KINTE[7:0]

R/W

NAME

ADR

Def

hex

CS KPROP H

NON

SNR

CS KP2[4:0]

CS KP1[4:3]

R/W

CS KROP L

CS KP1 [2:-0]

CS KP0[p4:0]

R/W

MT312C/CG Datasheet(PDF) 65 Page - Zarlink Semiconductor Inc

MT312C/CG Datasheet(HTML) 65 Page - Zarlink Semiconductor Inc

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