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MT312C/CG Datasheet(PDF) 64 Page - Zarlink Semiconductor Inc |
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MT312C/CG Datasheet(HTML) 64 Page - Zarlink Semiconductor Inc |
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64 / 90 page ![]() MT312 Secondary Registers for Test and De-Bugging 64 10.2.8 SNR Low Threshold Value. Register 48 (R/W) SNR THS LOW (48) Default value 90 dec. 5A hex. SNR THS SNR low threshold value. LOW[7:0] 10.2.9 SNR HIGH Threshold Value. Register 49 (R/W) SNR THS HIGH (49) Default value 70 dec. 46 hex. SNR THS SNR high threshold Change to 50 dec. 32 hex. after a full reset. HIGH[7:0] value. 10.2.10 Timing Synchronisation Sweep Rate. Register 50 (R/W) TS SW RATE (50) Default value 30 dec. 1E hex. TS SW Timing Synchronisation sweep rate. RATE[7:0] For DSS set the value to 20 dec. 14 hex. after a full reset. 10.2.11 Timing Synchronisation Sweep Limit Low. Register 51 (R/W) TS SW LIM Default value 64 dec. 40 hex. L (51) TS SW LIM L[7:0] Timing Synchronisation sweep limit low. 10.2.12 Timing Synchronisation Sweep Limit High. Register 52 (R/W) TS SW LIM H (52) Default value 132 dec. 84 hex. TS SW LIM Timing Synchronisation sweep limit high. H[7:0] 10.2.13 Carrier Synchronisation Sweep Rate 1. Register 53 (R/W) CS SW RATE 1 (53) Default value 32 dec. 20 hex. CS SW Carrier Synchronisation sweep rate 1. RATE 1[7:0] 10.2.14 Carrier Synchronisation Sweep Rate 2. Register 54 (R/W) CS SW Default value 72 dec. 48 hex. RATE 2 (54) CS SW Carrier Synchronisation sweep rate 2. RATE 2[7:0] |
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