MT312CSLASHCG datasheet(63/90 Pages) ZARLINK

63 / 90 page

Secondary Registers for Test and De-Bugging

MT312

10.2 Secondary Registers for Test and De-Bugging Read/Write Registers

10.2.1 AGC Initial Value. Register 40 (R/W)

AGC INIT (40)

Default value

59 dec.

3B hex.

AGC INIT[7:0]

Front End AGC initial value.

10.2.2 AGC Maximum Value. Register 42 (R/W)

AGC MAX (42)

Default value

255 dec.

FF hex.

AGC MAX[7:0]

Front End AGC maximum value.

10.2.3 AGC Minimum Value. Register 43 (R/W)

AGC MIN (43)

Default value

0 dec.

00 hex.

AGC MIN[7:0]

Front End AGC minimum value.

10.2.4 AGC Lock Threshold Value. Register 44 (R/W)

AGC LK TH (44)

Default value

10 dec.

0A hex.

AGC LK TH[7:0]

Front End AGC lock threshold value.

10.2.5 AGC Lock Threshold Value. Register 45 (R/W)

TS AGC LK TH (45)

Default value

30 dec.

1E hex.

TS AGC LK

Timing synchroniser ﬁne AGC lock threshold value.

TH[7:0]

10.2.6 AGC Power Setting Initial Value. Register 46 (R/W)

AGC PWR SET (46)

Default value

20 dec.

14 hex.

AGC PWR

AGC power setting initial value.

SET[7:0]

10.2.7 QPSK Miscellaneous. Register 47 (R/W)

QPSK MISC (47)

Default value

0 dec.

00 hex.

QPSK

Reserved, must be set low,

MISC[B7-0]

MT312C/CG Datasheet(PDF) 63 Page - Zarlink Semiconductor Inc

MT312C/CG Datasheet(HTML) 63 Page - Zarlink Semiconductor Inc

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