MT312CSLASHCG datasheet(71/90 Pages) ZARLINK

71 / 90 page

Secondary Registers for Test and De-Bugging

MT312

10.2.43 Byte Align Set up. Register 95 (R/W)

B7-6:

BA FSM[1:0]

Byte Align FSM mode.

B5-4:

MA MV[2:0] + 5 =

Byte Align majority voting.

B3-0:

BA UNLK[3:0] +3 =

Number of bad sync words to unlock the Byte Align. The default

10.2.44 Program Synchronising Byte. Register 98 (R/W)

PROG SYNC (98)

Default value

71 dec.

47 hex.

PROG SYNC[7:0 ]

If FEC SETUP[2] is high, use the PROG SYNC value to

synchronise MPEG data packets.

10.2.45 AFC Frequency Search Threshold. Register 99 (R/W)

AFC SEAR TH (99)

Default value

35 dec.

23 hex.

AFC SEAR TH[7:0]

10.2.46 Accumulator Differential Threshold. Register 100 (R/W)

CSACC DIFF TH (100)

Default value

32 dec.

20 hex.

CSACC DIFF TH[7:0]

10.2.47 QPSK Lock Control. Register 101 (R/W)

B7:

CS L LK

High = Use CS long lock.

B6:

TS L LK

High = Use TS long lock.

B5:

ACC CK

High = Disable Accumulator check option.

B4-0:

NUM PLD INT[4:0]

Maximum value allowed is 29.

NAME

ADR

Def

hex

BA SETUP

BA FSM[1:0]

BA MV[1:0]

BA UNLK[3:0]

R/W

NAME

ADR

Def

hex

QPSK LK CT

101

L LK

ACC

NUM PLD INT[4:0]

R/W

MT312C/CG Datasheet(PDF) 71 Page - Zarlink Semiconductor Inc

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