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MT312C/CG Datasheet(PDF) 23 Page - Zarlink Semiconductor Inc |
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MT312C/CG Datasheet(HTML) 23 Page - Zarlink Semiconductor Inc |
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23 / 90 page  Initialisation MT312 23 3.5.3 System Clock Frequency. Register 34 (R/W) SYS CLK[7:0] = System clock frequency * 2 in MHz. The SYS CLK register must be programmed to indicate the system clock frequency to the calculation unit. The maximum system clock frequency allowed is 90MHz. e.g. for a crystal frequency = 10MHz, if the PLL multiplication ratio is 9, The system clock frequency = 90MHz. Then SYS CLK[7:0] = 180. The system clock frequency is NOT affected by the setting of SYS CLK[7:0] register. 3.6 MT312 Initialisation Read Register 3.6.1 Identification. Register 126 (R) ID[7:0]: This register provides an identification number related to the MT312 version. NAME ADR B7 B6 B5 B4 B3 B2 B1 B0 Def hex SYS CLK 34 SYS CLK[7:0] - System clock frequency x2 in MHz R/W 00 NAME ADR B7 B6 B5 B4 B3 B2 B1 B0 Def hex ID 126 ID[7:0] Chip identification. R 03 |
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