MT312CSLASHCG datasheet(3/90 Pages) ZARLINK

3 / 90 page

Design Manual

MT312

Quick start overview

The MT312 is a QPSK/BPSK 1 to 45MBaud

demodulator and channel decoder for digital satellite

television transmissions compliant to both DVB-S

and DSS standards and other systems, such as

LMDS, that use the same architecture.

Command

Driven

Control

(CDC)

system

provided making the MT312 very simple to program.

After the tuner has been programmed to the required

frequency, to acquire a DVB transmission, the

MT312 requires a minimum of ﬁve registers to be

written. Activity ﬂow diagrams for initialisation and

basic channel change are included in section 2.

The MT312 provides a monitor of Bit Error Rate after

the QPSK module and also after the Viterbi module.

For receiver installation, a high speed scan or 'blind

search' mode is available. This allows all signals

from a given satellite to be evaluated for frequency,

symbol rate and convolutional coding scheme. The

phase of the IQ signals can be automatically

determined.

Full DiSEqC™ v2.2 is provided for both writing and

reading DiSEqC™ messages. Storage in registers

for up to eight data bytes sent and eight data bytes

received is provided.

Figure 3 - MT312 Functional Block Diagram

Analog

Ccontrol

Dual ADC

De-rotator

Decimation

Filteriing

Timing recovery

Matched filter

Phase recovery

DVB

DSS

FEC

Clock Generation

Acquisition

Control

I?C

Interface

Bus I/O

MPEG/

DSS

Packets

I I/P

Q I/P

Additional Features

•

2-wire bus microprocessor interface.

•

All digital clock and carrier recovery.

•

On-chip PLL clock generation using low cost 10

to 15MHz crystal.

•

3.3V operation.

•

80 pin MQFP package.

•

Low external component count.

•

Commercial temperature range 0 to 70°C.

Demodulator

•

BPSK or QPSK programmable.

•

Optional fast acquisition mode for low symbol

rates.

Viterbi

•

Programmable decoder rates 1/2, 2/3, 3/4, 5/6,

6/7, 7/8.

•

Automatic spectrum resolution of IQ phase.

•

Constraint length k=7.

•

Trace back depth 128.

•

Extensive SNR and BER monitors.

De-Interleaver

•

Compliant with DVB and DSS standards.

Reed Solomon

•

(204, 188) for DVB and (146,130) for DSS.

•

Reed Solomon Bit-error-rate monitor to indicate

Viterbi performance.

De-Scrambler

•

EBU speciﬁcation De-scrambler for DVB mode.

Outputs

•

MPEG transport parallel & serial output.

•

MPEG clock input for external synchronising of

MPEG data output.

•

Integrated MPEG2 TEI bit processing for DVB

only.

Application Support

•

Channel decoder system evaluation board.

•

Windows based evaluation software.

•

ANSI C generic software.

MT312C/CG Datasheet(PDF) 3 Page - Zarlink Semiconductor Inc

MT312C/CG Datasheet(HTML) 3 Page - Zarlink Semiconductor Inc

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