MT312CSLASHCG datasheet(32/90 Pages) ZARLINK

32 / 90 page

MT312 DiSEqC Control

This is the software (partial) reset for DISEQC2 module. If this is set to 1 in the DISEQC2 listen (or

receive) period, any listen operations will be aborted and DISEQC2 will wait until the end of the next

transmission to expect a reply.

Note that the host beginning the next DISEQC2 transmission will have a similar effect to writing bit 4.

B3:

Interrupt enable for bit B3 of DISEQC2 INT STAT register 118.

B2:

Interrupt enable for bit B2 of DISEQC2 INT STAT register 118.

B1:

Interrupt enable for bit B1 of DISEQC2 INT STAT register 118.

B0:

Interrupt enable for bit B0 of DISEQC2 INT STAT register 118.

Bits B0 and B3 are interrupt enables. These determine whether bits B0 to B3 of DISEQC2 INT (register 118,

see 33) have any impact on the pin IRQ 57 of the MT312.

Note that buffer overﬂow interrupt does not have an interrupt enable and hence this cannot be brought out to

the IRQ pin.

5.2.5 DiSEqCTM 2 Control 2. Registers 122 (R/W)

B[7:5]:

MIN PULS PER

Minimum Pulse Period.

B[4-2]:

TONE EXT PER

Tone Impulse Extended Period.

NAME

ADR

Def

hex

DISEQC2

CTRL2

122

MIN PULS PER

TONE EXT PER

MAX TONE

PER

R/W

B7-5:

MIN PULS PER

000

24 * DISEQC RATIO

001

25 * DISEQC RATIO

010

26 * DISEQC RATIO

011

27 * DISEQC RATIO

100

28 * DISEQC RATIO

101

29 * DISEQC RATIO

110

30 * DISEQC RATIO

(default)

111

31 * DISEQC RATIO

B1-0:

TONE EXT PER

000

7 * DISEQC RATIO

001

8 * DISEQC RATIO

010

9 * DISEQC RATIO

011

10 * DISEQC RATIO

100

11 * DISEQC RATIO

MT312C/CG Datasheet(PDF) 32 Page - Zarlink Semiconductor Inc

MT312C/CG Datasheet(HTML) 32 Page - Zarlink Semiconductor Inc

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