MT312CSLASHCG datasheet(72/90 Pages) ZARLINK

72 / 90 page

MT312 Secondary Registers for Test and De-Bugging

10.2.48 QPSK State Control. Register 102 (R/W)

B7:

HLD ST

High = Hold state.

B6:

AFC RS

High = AFC reset.

B5:

M S RS

High = Mixer scan reset.

B4:

NXT FR

High = Get next frequency.

B3:

FCE ST

High = Force state.

B2-0:

FORCED ST[2:0]

Forced state.

10.2.49 QPSK Reset. Register 104 (R/W)

B7-6:

Reserved Must be set low.

B5:

REL QP

High = Release QPSK FSM.

B4:

PR QP

High = Partial reset FSM (applies to QPSK control).

B3:

PR CS

High = Partial reset carrier synchroniser

B2:

PR TS

High = Partial reset timing synchroniser (includes ﬁne AGC).

B1:

PR FE

High = Partial reset front-end logic.

B0:

PR AGC

High = Partial reset analogue AGC.

10.2.50 QPSK Test Control. Register 105 (R/W)

QPSK TST CT (105)

Default value

0 dec.

00 hex.

QPSK TEST CTRL[7:0]

For factory test purposes only.

NAME

ADR

Def

hex

QPSK ST CT

102

HLD

AFC

M S

NXT

FCE

FORCED ST[2:0]

R/W

NAME

ADR

Def

hex

QPSK RESET

104

Reserved

REL

AGC

R/W

MT312C/CG Datasheet(PDF) 72 Page - Zarlink Semiconductor Inc

MT312C/CG Datasheet(HTML) 72 Page - Zarlink Semiconductor Inc

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