MT312CSLASHCG datasheet(80/90 Pages) ZARLINK

80 / 90 page

MT312 Electrical Characteristics

12.5 MT312 Pinout Description

Name

Description

I/O

Note

4,5,6,7,8,11,12

ADDR[7:1]

Primary 2-wire bus address deﬁning pins

I/O

CMOS

3.3

MICLK

MPEG clock input used to generate

MOCLK. Enabled when both register 96

bit 7 and register 97 bit 7 are set high. In

this mode, MICLK must be continuous.

ICMOS

5 1

TESTCLK

External ADC mode clock.

PECL

Tri-

state

3.3

XTI

Crystal clock input or external reference

clock input.

CMOS

3.3

XTO

Crystal output. An internal feedback

resistor to XTI is included

CMOS

3.3

PLL1

Phase Locked Loop test output

VRT

ADC Voltage top reference level

IREF

I channel de-coupling input

ISINGP

I channel input

No connection

VRM

ADC Voltage middle reference level

QSINGP

Q channel input

QREF

Q channel de-coupling input

VRB

ADC Voltage bottom reference level

RREF

Bias level

TEST1

For factory test only. This pin must be

connected to VSS in normal operation

CMOS

3.3

TEST2

For factory test only. This pin must be

connected to VSS in normal operation

CMOS

3.3

AGC

AGC sigma-delta output

Open

drain

5 1

46,45,44

GPP[2:0]

(DISEQC2)

General Purpose Port for tuner control,

GPP0 = secondary CLK2,

GPP1 = secondary DATA2,

GPP2 = DiSEqC™ v2.2 input signal.

I/O

Open

drain

5 1

DISEQC1

DiSEqC™ Horizontal/Vertical control

CMOS

3.3

DISEQC0

DiSEqCTM 22kHz output

CMOS

3.3

RESET

Active low reset input

CMOS

5 1

STATUS

Audio BER or Status output, register

deﬁned

CMOS

3.3

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