MT312CSLASHCG datasheet(60/90 Pages) ZARLINK

60 / 90 page

MT312 MPEG Packet Data Output

Note:

the BKERR signal on pin 75 can be inverted by setting the BKERIV bit 6 of OP CTRL register 96, see

page 37.

B6-4:

Reserved, not used.

B3-0:

MON CTRL[3:0] selects which pair of registers will be read from MONITOR H & L registers 123 and

124, (see section 6.10 on page 48).

I and Q input samples when MON CTRL[3:0] = 0.

DC offset in the I and Q inputs when MON CTRL[3:0] = 1.

Symbol Rate when MON CTRL[3:0] = 3, (see section 6.2.4 Monitor Registers. Registers 123 - 124 (R)).

Decimation ratio when MON CTRL[3:0] = 5, (see 6.2.4 Monitor Registers. Registers 123 - 124 (R)).

Timing synchroniser frequency lock detector value when MON CTRL[3:0] = 6, (see section 6.2.4 Monitor

Registers. Registers 123 - 124 (R)).

Timing lock detector value when MON CTRL[3:0] = 7, (see section 6.2.4 Monitor Registers. Registers 123 - 124

(R)).

Phase lock detector value when MON CTRL[3:0] = 8, (see section 6.2.4 Monitor Registers. Registers 123 - 124

(R)).

The remaining settings of MON CTRL[3:0] are either reserved for diagnostic purposes or not used.

MON CTRL[3:0]

MONITOR H (123)

MONITOR L (124)

CS SYM I

CS SYM Q

DC OFFSET I

DC OFFSET Q

Reserved

MBAUD OP H

MBAUD OP L

Reserved

DEC RATIO[15:13]

and the rest reserved

Reserved

M FLD[7:0]

M FLD7:0]

M TLD H

M TLD L

M PLD H

M PLD L

15 - 9

Not used

MT312C/CG Datasheet(PDF) 60 Page - Zarlink Semiconductor Inc

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