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MT312C/CG Datasheet(PDF) 62 Page - Zarlink Semiconductor Inc |
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MT312C/CG Datasheet(HTML) 62 Page - Zarlink Semiconductor Inc |
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62 / 90 page  MT312 Secondary Registers for Test and De-Bugging 62 NAME ADR B7 B6 B5 B4 B3 B2 B1 B0 Def hex Page PLD OUTLK0 72 PLD OUTLK1[7:0] R/W 7E 66 PLD INLK3 73 Reserved PLD INLK3[9:4] R/W 01 67 PLD INLK2 74 PLD INLK3[3:0] PLD INLK2[9:6] R/W A0 67 PLD INLK1 75 PLD INLK2[5:0] PLD INLK1 [9:8] R/W 68 67 PLD INLK0 76 PLD INLK1[7:0] R/W 1A 67 PLD ACC TIME 77 CS PLD MPLEN[3:0] LOSSLOCK INT SW[3:0] R/W 48 67 SWEEP PAR 78 SW LIM SC[1:0] TS NR SWEEP[2:0] CS NR SWEEP[2:0] R/W 49 68 STARTUP TIME 79 STARTUP INTERVAL[7:0] R/W 30 68 LOSSLOCK TH 80 LOSSLOCK TH SPUR[3:0] LOSSLOCK TH SW[3:0] R/W 21 68 FEC LOCK TM 81 FEC LOCK TIME[7:0] R/W 20 68 LOSSLOCK TM 82 LOSSLOCK TIME[7:0] R/W 10 69 VIT ERRPER H 83 VIT ERRPER[23:16] Viterbi error period (high byte) R/W FF 69 VIT ERRPER M 84 VIT ERRPER[15:8] Viterbi error period (middle byte) R/W FF 69 VIT ERRPER L 85 VIT ERRPER[7:0] Viterbi error period (low byte) R/W FF 69 VIT SETUP 86 FR AL TM O[1:0] SRCH CYC [1:0] SEARCH START [2:0] EX F LK R/W 34 69 VIT REF0 87 VIT REF0[7:0] Viterbi reference byte 0 R/W 80 69 VIT REF1 88 VIT REF1[7:0] Viterbi reference byte 1 R/W 14 70 VIT REF2 89 VIT REF2[7:0] Viterbi reference byte 2 R/W 0A 70 VIT REF3 90 VIT REF3[7:0] Viterbi reference byte 3 R/W 06 70 VIT REF4 91 VIT REF4[7:0] Viterbi reference byte 4 R/W 04 70 VIT REF5 92 VIT REF5[7:0] Viterbi reference byte 5 R/W 02 70 VIT REF6 93 VIT REF6[7:0] Viterbi reference byte 6 R/W 01 70 VIT MAXERR 94 VIT MAXERR [7:0] Viterbi max. error bit count R/W FF 70 BA SETUPT 95 BA FSM[1:0] BA MV [1:0] BA UNLK[3:0] R/W D4 71 PROG SYNC 98 PROG SYNC BYTE[7:0] Enabled by FEC SETUP [2] R/W 47 71 AFC SEAR TH 99 AFC SEAR TH[7:0] R/W 23 71 CSACC DIF TH 100 ACC DIF TH[7:0] R/W 20 71 QPSK LK CT 101 CS L LK TS L LK ACC CK NUM PLD INT[4:0] R/W 04 71 QPSK ST CT 102 HLD ST AFC RS M S RS NXT FR FCE ST FORCED ST[2:0] R/W 00 72 QPSK RESET 104 Reserved REL QP PR QP PR CS PR TS PR FE PR AGC R/W 00 72 QPSK TST CT 105 QPSK TEST CTRL[7:0] R/W 00 72 QPSK TST ST 106 QPSK TEST TS[7:0] R/W 00 73 TEST MODE 125 Test mode R/W 00 73 Read/Write Secondary register map (continued) |
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