MT312CSLASHCG datasheet(52/90 Pages) ZARLINK

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MT312 Automatic Gain Control

8 Automatic Gain Control

8.1 Automatic Gain Control Read/Write Registers

8.1.1 AGC Control. Register 39 (R/W)

B7:

Reserved.

Must be set low.

B6:

Reserved.

Must be set low.

B5-4:

AGC SD[1:0]

Sigma Delta clock decimation ratio related to system clock.

AGC control output is a pulse density modulated output created by a sigma-delta modulator. To reduce power

consumption this is not clocked at the full system clock rate. The frequency at which this is clocked is the

system clock divided by the decimation factor in Table 6.

B3-1:

AGC BW[2:0]

Front End AGC bandwidth (retain default value of 3).

B0:

AGC SL Analogue AGC slope

High = positive slope i.e. RF gain proportional to AGC voltage.

Low = negative slope i.e. RF gain inversely proportional to AGC voltage (default).

8.1.2 AGC REF Reference Value. Register 41 (R/W)

AGC REF[7:0]

Front End AGC reference value.

The AGC loop control in MT312 is designed to bring the mean square value of the I signal (or the Q signal) at

the ADC output (prior to any digital ﬁltering) to the value set by the AGC REF register.

NAME

ADR

Def

hex

AGC CTRL

Reserved

AGC SD[1:0]

AGC BW[2:0]

AGC

R/W

AGC SD[1:0]

Decimation

Table 4 - Sigma Delta clock decimation ratio programming

NAME

ADR

Def

hex

AGC REF

AGC REF[7:0] AGC reference level

R/W

MT312C/CG Datasheet(PDF) 52 Page - Zarlink Semiconductor Inc

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