MT312CSLASHCG datasheet(5/90 Pages) ZARLINK

5 / 90 page

Contents

MT312

DiSEqC Control ...................................................................................................... 29

5.1

Screen Printouts of DiSEqC™ Waveforms ........................................................................................ 29

5.2

DiSEqC Control Read/Write Registers ............................................................................................... 30

5.2.1

DiSEqC™ Mode Control. Register 22 (R/W) .............................................................................. 30

5.2.2

DiSEqC(tm) Ratio. Register 35 (R/W) ........................................................................................ 30

5.2.3

DiSEqC™ Instruction (R/W). Register 36 (R/W) ........................................................................ 31

5.2.4

DiSEqC™ 2 Control 1. Registers 121 (R/W) .............................................................................. 31

5.2.5

DiSEqCTM 2 Control 2. Registers 122 (R/W) ............................................................................ 32

5.3

DiSEqC Control Read Registers ........................................................................................................ 33

5.3.1

DiSEqC™M 2 Interrupt Indicators. Register 118 (R) .................................................................. 33

5.3.2

DiSEqC™M 2 Status Indicators. Register 119 (R) ..................................................................... 34

5.3.3

DiSEqC™ 2 FIFO. Register 120 (R) ........................................................................................... 34

QPSK demodulator ................................................................................................ 36

6.1

QPSK Demodulator Read/Write Registers ........................................................................................ 36

6.1.1

Symbol Rate. Registers 23 - 24 (R/W) ....................................................................................... 36

6.1.2

Viterbi mode. Register 25 (R/W) ................................................................................................. 38

6.1.3

QPSK Control. Register 26 (R/W) .............................................................................................. 39

6.1.4

Go Command. Register 27 (R/W) .............................................................................................. 40

6.1.5

QPSK Interrupt Output Enable. Registers 28 - 30 (R/W) ........................................................... 40

6.1.6

QPSK STATUS Output Enable. Register 32 (R/W) .................................................................... 41

6.2

QPSK Demodulator Read Registers .................................................................................................. 42

6.2.1

QPSK Interrupt. Registers 0 - 2 (R) ............................................................................................ 42

6.2.2

QPSK Status. Registers 4 - 5 (R) ............................................................................................... 44

6.2.3

Symbol Rate Output. Registers 116 - 117 (R) ............................................................................ 44

6.2.4

Monitor Registers. Registers 123 - 124 (R) ................................................................................ 45

Forward Error Correction ...................................................................................... 46

7.1

Forward Error Correction Read/Write Registers ................................................................................ 47

7.1.1

FEC Interrupt Enable. Register 31 (R/W) ................................................................................... 47

7.1.2

FEC STATUS Output Enable. Register 33 (R/W) ...................................................................... 47

7.1.3

FEC Set Up. Register 97 (R/W) .................................................................................................. 48

7.2

Forward Error Correction Read Registers .......................................................................................... 48

7.2.1

FEC Interrupt. Register 3 (R) ...................................................................................................... 48

7.2.2

FEC Status. Register 6 (R) ......................................................................................................... 49

7.2.3

Measured Signal to Noise Ratio. Registers 9 - 10 (R) ................................................................ 49

7.2.4

Viterbi Error Count at Viterbi Input. Registers 11 - 13 (R) .......................................................... 50

7.2.5

Reed Solomon Bit Errors Corrected. Registers 14 - 16 (R) ........................................................ 50

7.2.6

Reed Solomon Uncorrected block Errors. Registers 17 - 18 (R) ................................................ 51

Automatic Gain Control ........................................................................................ 52

8.1

Automatic Gain Control Read/Write Registers ................................................................................... 52

8.1.1

AGC Control. Register 39 (R/W) ................................................................................................ 52

8.1.2

AGC REF Reference Value. Register 41 (R/W) ......................................................................... 52

8.2

Automatic Gain Control Read Registers ............................................................................................ 53

8.2.1

Measured Signal Level at MT312 Input. Register 19 (R) ........................................................... 53

8.2.2

Measured AGC Feed Back Value. Registers 108 - 110 (R) ....................................................... 53

MPEG Packet Data Ouput ..................................................................................... 54

9.1

MPEG Clock Modes ........................................................................................................................... 54

9.2

Data Output Header Format - DVB only ............................................................................................ 55

9.3

MPEG/DSS Data Output Signals ....................................................................................................... 56

9.4

Data output timing .............................................................................................................................. 58

9.5

MPEG Packet Data Output Read/Write Registers ............................................................................. 59

9.5.1

Output Data Control. Register 96 (R/W) ..................................................................................... 59

9.5.2

Monitor Control. Register 103 (R/W) .......................................................................................... 59

MT312C/CG Datasheet(PDF) 5 Page - Zarlink Semiconductor Inc

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