MT312CSLASHCG datasheet(35/90 Pages) ZARLINK

Part #	MT312C/CG

Description	Satellite Channel Decoder

PDF	90 Pages

Scroll/Zoom	100%

Manufacturer	ZARLINK [Zarlink Semiconductor Inc]

Direct Link	http://www.zarlink.com

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35 / 90 page

DiSEqC Control

MT312

Refer to preceding section for buffer overﬂow.

The received bytes are read from this location with 2-wire bus auto-increment bit set to zero. The received

bytes will be available in the order received, i.e. the buffer is a First In First Out (FIFO) memory.

Note that two read operations are needed for each byte. The ﬁrst read operation will give the data byte and the

second will provide the associated parity bit(B0) and the parity-error bit(B1), the other 6 bits will be zero. For

example, if four bytes are received, then eight read operations (with auto-increment bit set to zero) are needed

to get all data bytes as well as the parity bits.

The number of bytes received is given by bits B3-0 of DISEQC2 STATUS BYTES register 119.

NAME

ADR

Def

hex

DISEQC2 FIFO

120

Reserved

Par

error

Par

bit

R00

MT312C/CG Datasheet(PDF) 35 Page - Zarlink Semiconductor Inc