MT312CSLASHCG datasheet(19/90 Pages) ZARLINK

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Initialisation

MT312

3 MT312 Initialisation

3.1 The Conﬁguration Register (127)

CONFIG[B7-0]: This register is for setting up the

MT312. It must be loaded ﬁrst before any other

the RESET pin being pulled low. After loading this

writing to the RESET register. During this wait

period, the tuner may be programmed via the

General Purpose Port. Note that the GPP register

occupies the address space before the RESET

CONFIG[B7]: 312 ENHigh = MT312 enable.

Low = MT312 disable to save power.

CONFIG[B6-5]: DSS BDSS A

0: DVB mode

1: DSS mode 1 - code rate 2/3

0: DSS mode 2 - code rate 6/7

1: DSS Code Rate search

If both DSS A and DSS B are set high, the MT312

will search for the code rate in DSS mode. If either of

the DSS A or DSS B are set high, the Symbol rate is

automatically set to 20Mbaud and SYM RATE

registers (23 & 24) are ignored. The matched ﬁlter

root-raised-cosine roll-off is set to 0.20 and bit B0 of

QPSK CTRL (26) is ignored. Also, any code rate

programmed into VIT MODE register (25) and VIT

SETUP register (86) will be ignored.

Also in DSS mode TS SW RATE register (50) must

be set to 20, see 10.2.10 Timing Synchronisation

Sweep Rate. Register 50 (R/W).

CONFIG[B4]:

BPSK High = BPSK

Low = QPSK

CONFIG[B3-2]: PLL FACTOR[1:0]:

B3-2

Multiplication factor

00:

01:

10:

11:

CONFIG[B1]:

CRYS15

High = 15MHz crystal.

Low = 10MHz crystal.

CONFIG[B0]:

ADCEXT

High = ADC external.

Low = ADC internal.

e.g. For a crystal frequency of 10MHz, a system

clock frequency of 60MHz, the PLL ratio will be 6,

requiring the PLL FACTOR[1:0] = 2.

For QPSK reception and ADC internal, the MT312 is

enabled by writing 88 hex to register 127.

MT312 computes the System clock frequency using

bits B3-B1 above. This frequency is used internally

for computing parameters needed for acquiring the

QPSK signal.

It is possible to use a crystal frequency other than 10

or 15 MHz. As an example, let the crystal frequency

be 10.25MHz and the PLL multiplication factor be 6.

Then B3 is set to 1 and B2 to 0. Bit B1 may be given

an arbitrary value (0 or 1). The external software

must compute the system clock frequency and load

this value (multiplied by 2) to the SYS CLK register

(Address 34). In the above example, the system

clock frequency is 61.5 MHz and hence the value

123 has to be loaded into SYS CLK register.

The QPSK demodulator checks the SYS CLK

this as the system clock frequency, for internal

calculations mentioned above. If this register is zero

(which is the default setting), QPSK demodulator

works out the system clock frequency from bits B3-

B1 of the CONFIG register assuming that the crystal

frequency is either 10 or 15 MHz, as deﬁned by bit

B1.

3.2 Power Supplies

To avoid the possibility of destructive latch-up, the

CVDD supply must never, at any time during power-

up, exceed 0·5V above the VDD supply and must

also remain within the absolute maximum ratings,

see section 12.2 on page 78.

In general therefore, the VDD supply should be

established ahead of, or simultaneously with the

CVDD supply.

VDD

CVDD

RESET

Osc

SLEEP

~1ms typ.

ADDR[7:1]

Don’t care

Figure 14 - MT351 power-up sequence

MT312C/CG Datasheet(PDF) 19 Page - Zarlink Semiconductor Inc

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