DM504 datasheet(175/211 Pages) TI1

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The resistance Rs of a plane conductor

for a unit length and unit width is called

the

(ohms per square).

surface resistivity

σ ×

Rs =

R = Rs

SPRS91v_PCB_STATIC_01

vdd

vdd_mpu

vss

SPRS91v_PCB_PHYS_05

175

DM504

www.ti.com

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Applications, Implementation, and Layout

Figure 7-2. Coplanar Shielding of Power Net Using Ground Guard-band

7.2.3

Step 3: Static Analysis

Delivering reliable power to circuits is always of critical importance because voltage drops (also known as

IR drops) can happen at every level within an electronic system, on-chip, within a package, and across the

board. Robust system performance can only be ensured by understanding how the system elements will

perform under typical stressful Use Cases. Therefore, it is a good practice to perform a Static or DC

Analysis.

Static or DC analysis and design methodology results in a PDN design that minimizes voltage or IR drops

across power and ground planes, traces and vias. This ensures the application processor’s internal

transistors will be operating within their specified voltage ranges for proper functionality. The amount of IR

drop that will be encounter is based upon amount power drawn for a desired Use Case and PCB trace

(widths, geometry and number of parallel traces) and via (size, type and number) characteristics.

Components that are distant from their power source are particularly susceptible to IR drop. Designs that

rely on battery power must minimize voltage drops to avoid unacceptable power loss that can negatively

impact system performance. Early assessments a PDN’s static (DC) performance helps to determine

basic power distribution parameters such as best system input power point, optimal PCB layer stackup,

and copper area needed for load currents.

Figure 7-3. Depiction of Sheet Resistivity and Resistance

Ohm’s Law (V = I × R) relates conduction current to voltage drop. At DC, the relation coefficient is a

constant and represents the resistance of the conductor. Even current carrying conductors will dissipate

power at high currents even though their resistance may be very small. Both voltage drop and power

dissipation are proportional to the resistance of the conductor.

Figure 7-4 shows a PCB-level static IR drop budget defined between the power management device

(PMIC) pins and the application processor’s balls when the PMIC is supplying power.

•

It is highly recommended to physically place the PMIC as close as possible to the processor and on

the same side. The orientation of the PMIC vs. processor should be aligned to minimize distance for

the highest current rail.

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