DM504 datasheet(174/211 Pages) TI1

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DIE

Trace

Capacitor

Via

Note: 1. BGA via pair loop inductance

2. Power/Ground net spreading inductance

3. Capacitor trace inductance

Loop inductance

Power/Ground

Ground/Power

SPRS91v_PCB_STACKUP_01

174

DM504

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Applications, Implementation, and Layout

Figure 7-1. Minimize Loop Inductance With Proper Layer Assignment

The placement of power and ground planes in the PCB stackup (determined by layer assignment) has a

significant impact on the parasitic inductances of power current path as shown in Figure 7-1. For this

reason, it is recommended to consider layer order in the early stages of the PCB PDN design cycle,

putting high-priority supplies in the top half of the stackup (assuming high load and priority components

are mounted on the top-side of PCB) and low-priority supplies in the bottom half of the stackup as shown

in the examples below (vias have parasitic inductances which impact the bottom layers more, so it is

advised to put the sensitive and high-priority power supplies on the top/same layers).

7.2.2

Step 2: Physical Placement

A critical step in designing an optimized PDN is that proper care must be taken to making sure that the

initial floor planning of the PCB layout is done with good power integrity design guidelines in mind. The

following points are important for optimizing a PCB’s PDN:

•

Minimizing the physical distance between power sources and key high load components is the first

step toward optimization. Placing source and load components on the same side of the PCB is

desirable. This will minimize via inductance impact for high current loads and steps

•

External trace routing between components must be as wide as possible. The wider the traces, the

lower the DC resistance and consequently the lower the static IR drop.

•

Whenever possible for the internal layers (routing and plane), wide traces and copper area fills are

preferred for PDN layout. The routing of power nets in plane provide for more interplane capacitance

and improved high frequency performance of the PDN.

•

Whenever possible, use a via to component pin/pad ratio of 1:1 or better (i.e. especially decoupling

capacitors, power inductors and current sensing resistors). Do not share vias among multiple

capacitors for connecting power supply and ground planes.

•

Placement of vias must be as close as possible or even within a component’s solder pad if the PCB

technology you are using provides this capability.

•

To avoid any “ampacity” issue – maximum current-carrying capacity of each transitional via should be

evaluated to determine the appropriate number of vias required to connect components.

Adding vias to bring the “via-to-pad” ratio to 1:1 will improve PDN performance.

•

For noise sensitive power supplies (i.e. Phase Lock-Loops, analog signals like audio and video), a Gnd

shield can be used to isolate coplanar supplies that may have high step currents or high frequency

switching transitions from coupling into low-noise supplies.

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