DM504 datasheet(172/211 Pages) TI1

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DM504

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Applications, Implementation, and Layout

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test design implementation to confirm system functionality.

7.1

Introduction

This chapter is intended to communicate, guide and illustrate a PCB design strategy resulting in a PCB

that can support TI’s latest Application Processor. This Processor is a high-performance processor

designed for automotive Infotainment based on enhanced OMAP™ architecture integrated on a 28-nm

CMOS process technology.

These guidelines first focus on designing a robust Power Delivery Network (PDN) which is essential to

achieve the desirable high performance processing available on Device. The general principles and step-

by-step approach for implementing good power integrity (PI) with specific requirements will be described

for the key Device power domains.

TI strongly believes that simulating a PCB’s proposed PDN is required for first pass PCB design success.

Key Device processor high-current power domains need to be evaluated for Power Rail IR Drop,

Decoupling Capacitor Loop-Inductance and Power Rail Target Impedance. Only then can a PCB’s PDN

performance be truly accessed by comparing these model PI parameters vs. TI’s recommended values.

Ultimately for any high-volume product, TI recommends conducting a “Processor PDN Validation” test on

prototype PCBs across processor “split lots” to verify PDN robustness meets desired performance goals

for each customer’s worst-case scenario. Please contact your TI representative to receive guidance on

PDN PI modeling and validation testing.

Likewise, the methodology and requirements needed to route Device high-speed, differential interfaces ,

single-ended interfaces (i.e. DDR3, QSPI) and general purpose interfaces using LVCMOS drivers that

meet timing requirements while minimizing signal integrity (SI) distortions on the PCB’s signaling traces.

Signal trace lengths and flight times are aligned with FR-4 standard specification for PCBs.

Several different PCB layout stack-up examples have been presented to illustrate a typical number of

layers, signal assignments and controlled impedance requirements. Different Device interface signals

demand more or less complexity for routing and controlled impedance stack-ups. Optimizing the PCB’s

PDN stack-up needs with all of these different types of signal interfaces will ultimately determine the final

layer count and layer assignments in each customer’s PCB design.

This guideline must be used as a supplement in complement to TI’s Application Processor, Power

Management IC (PMIC) and Audio Companion components along with other TI component technical

documentation (i.e. Technical Reference Manual, Data Manual, Data Sheets, Silicon Errata, Pin-Out

Spreadsheet, Application Notes, etc.).

NOTE

Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or

statutory, including any implied warranty of merchantability of fitness for a specific purpose,

for customer boards. The data described in this appendix are intended as guidelines only.

NOTE

These PCB guidelines are in a draft maturity and consequently, are subject to change

depending on design verification testing conducted during IC development and validation.

Note also that any references to Application Processor’s ballout or pin muxing are subject to

change following the processor’s ballout maturity.

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