DM504 datasheet(168/211 Pages) TI1

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DM504

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Detailed Description

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32-bit time base counter

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4-event time-stamp registers (each 32 bits)

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Edge polarity selection for up to four sequenced time-stamp capture events

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Interrupt on either of the four events

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Single shot capture of up to four event time-stamps

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Continuous mode capture of time-stamps in a four-deep circular buffer

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Absolute time-stamp capture

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Difference (Delta) mode time-stamp capture

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All above resources dedicated to a single input pin

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When not used in capture mode, the ECAP module can be configured as a single channel PWM output

For more information, see section Enhanced Capture (eCAP) Module in chapter Pulse-Width Modulation

Subsystem of the device TRM.

6.10.18 eQEP

A single track of slots patterns the periphery of an incremental encoder disk. These slots create an

alternating pattern of dark and light lines. The disk count is defined as the number of dark/light line pairs

that occur per revolution (lines per revolution). As a rule, a second track is added to generate a signal that

occurs once per revolution (index signal: QEPI), which can be used to indicate an absolute position.

Encoder manufacturers identify the index pulse using different terms such as index, marker, home

position, and zero reference.

To derive direction information, the lines on the disk are read out by two different photo-elements that

"look" at the disk pattern with a mechanical shift of 1/4 the pitch of a line pair between them. This shift is

realized with a reticle or mask that restricts the view of the photo-element to the desired part of the disk

lines. As the disk rotates, the two photo-elements generate signals that are shifted 90 degrees out of

phase from each other. These are commonly called the quadrature QEPA and QEPB signals. The

clockwise direction for most encoders is defined as the QEPA channel going positive before the QEPB

channel.

The encoder wheel typically makes one revolution for every revolution of the motor or the wheel may be at

a geared rotation ratio with respect to the motor. Therefore, the frequency of the digital signal coming from

the QEPA and QEPB outputs varies proportionally with the velocity of the motor. For example, a 2000-line

encoder directly coupled to a motor running at 5000 revolutions per minute (rpm) results in a frequency of

166.6 KHz, so by measuring the frequency of either the QEPA or QEPB output, the processor can

determine the velocity of the motor.

For more information, see section Enhanced Quadrature Encoder Pulse (eQEP) Module in chapter Pulse-

Width Modulation Subsystem of the device TRM.

6.11 On-Chip Debug

Debugging a system that contains an embedded processor involves an environment that connects high-

level debugging software running on a host computer to a low-level debug interface supported by the

target device. Between these levels, a debug and trace controller (DTC) facilitates communication

between the host debugger and the debug support logic on the target chip.

The DTC is a combination of hardware and software that connects the host debugger to the target system.

The DTC uses one or more hardware interfaces and/or protocols to convert actions dictated by the

debugger user to JTAG® commands and scans that execute the core hardware.

The debug software and hardware components let the user control multiple central processing unit (CPU)

cores embedded in the device in a global or local manner. This environment provides:

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Synchronized global starting and stopping of multiple processors

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Starting and stopping of an individual processor

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