DM504 datasheet(169/211 Pages) TI1

169 / 211 page

169

DM504

www.ti.com

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

Submit Documentation Feedback

Detailed Description

•

Each processor can generate triggers that can be used to alter the execution flow of other processors

System topics include but are not limited to:

•

System clocking and power-down issues

•

Interconnection of multiple devices

•

Trigger channels

The device deploys Texas Instrument's CTools debug technology for on-chip debug and trace support. It

provides the following features:

•

External debug interfaces:

–

Primary debug interface - IEEE1149.1 (JTAG) or IEEE1149.7 (complementary superset of JTAG)

•

Used for debugger connection

•

Default mode is IEEE1149.1 but debugger can switch to IEEE1149.7 via an IEEE1149.7

adapter module

•

Controls ICEPick™ (generic test access port [TAP] for dynamic TAP insertion) to allow the

debugger to access several debug resources through its secondary (output) JTAG ports (for

more information, see section ICEPick Secondary TAPs in chapter On-Chip Debug Support of

the Device TRM).

–

Debug (trace) port

•

Can be used to export processor or system trace off-chip (to an external trace receiver)

•

Can be used for cross-triggering with an external device

•

Configured through debug resources manager (DRM) module instantiated in the debug

subsystem

•

For more information about debug (trace) port, see sections Debug (Trace) Port and Concurrent

Debug Modes in chapter On-Chip Debug Support of the Device TRM.

•

JTAG based processor debug on:

–

C66x in DSP1

–

Cortex-M4 (x2) in IPU

–

ARP32 in EVE

•

Dynamic TAP insertion

–

Controlled by ICEPick

–

For more information, see section Dynamic TAP Insertion in chapter On-Chip Debug Support

•

Power and clock management

–

Debugger can get the status of the power domain associated to each TAP.

–

Debugger may prevent the application software switching off the power domain.

–

Application power management behavior can be preserved during debug across power transitions.

–

For more information, see section Power and Clock Management in chapter On-Chip Debug

Support of the Device TRM.

•

Reset management

–

Debugger can configure ICEPick to assert, block, or extend the reset of a given subsystem.

–

For more information, see section Reset Management in chapter On-Chip Debug Support of the

Device TRM.

DM504 Datasheet(PDF) 169 Page - Texas Instruments

DM504 Datasheet(HTML) 169 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL