DM504 datasheet(173/211 Pages) TI1

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DM504

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SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Applications, Implementation, and Layout

7.1.1

Initial Requirements and Guidelines

Unless otherwise specified, the characteristic impedance for single-ended interfaces is recommended to

be between 35 Ω and 65 Ω to minimize the overshoot or undershoot on far-end loads.

Characteristic impedance for differential interfaces must be routed as differential traces on the same layer.

The trace width and spacing must be chosen to yield the recommended differential impedance. For more

information see Section 7.5.1.

The PDN must be optimized for low trace resistance and low trace inductance for all high-current power

nets from PMIC to the device.

An external interface using a connector must be protected following the IEC61000-4-2 level 4 system

ESD.

7.2

Power Optimizations

This section describes the necessary steps for designing a robust Power Distribution Network (PDN):

•

Section 7.2.1, Step 1: PCB Stack-up

•

Section 7.2.2, Step 2: Physical Placement

•

Section 7.2.3, Step 3: Static Analysis

•

Section 7.2.4, Step 4: Frequency Analysis

7.2.1

Step 1: PCB Stack-up

The PCB stack-up (layer assignment) is an important factor in determining the optimal performance of the

power distribution system. An optimized PCB stack-up for higher power integrity performance can be

achieved by following these recommendations:

•

Power and ground plane pairs must be closely coupled together. The capacitance formed between the

planes can decouple the power supply at high frequencies. Whenever possible, the power and ground

planes must be solid to provide continuous return path for return current.

•

Use a thin dielectric between the power and ground plane pair. Capacitance is inversely proportional to

the separation of the plane pair. Minimizing the separation distance (the dielectric thickness)

maximizes the capacitance.

•

Optimize the power and ground plane pair carrying high current supplies to key component power

domains as close as possible to the same surface where these components are placed (see Figure 7-

1). This will help to minimize “loop inductance” encountered between supply decoupling capacitors and

component supply inputs and between power and ground plane pairs.

NOTE

1-2oz Cu weight for power / ground plane is preferred to enable better PCB heat spreading,

helping to reduce Processor junction temperatures. In addition, it is preferable to have the

power / ground planes be adjacent to the PCB surface on which the Processor is mounted.

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