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DM504 Datasheet(PDF) 192 Page - Texas Instruments |
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DM504 Datasheet(HTML) 192 Page - Texas Instruments |
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192 / 211 page ![]() 192 DM504 SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017 www.ti.com Submit Documentation Feedback Applications, Implementation, and Layout Copyright © 2016–2017, Texas Instruments Incorporated IR Drop: vdd_dspeve Figure 7-16. vdd_dspeve Voltage/IR Drop [All Layers] Dynamic analysis of this PCB design for the CORE power domain determined the vdd_dspeve decoupling capacitor loop inductance and impedance vs frequency analysis shown below. As you can see, the loop inductance values ranged from 0.68 –1.79nH and were less than maximum 2.0nH recommended. Table 7-8. Decoupling Design Detail Summary Cap Reference Description Loop Inductacne at 50MHz [nH] Footprint Types PCB Side Distance to Ball-Field [mils] Value Size C5101 0.73 2vWEE Bottom 82 0.1 0402 C5100 0.78 2vWEE Bottom 107 0.1 0402 C5085 0.84 2vWEE Bottom 35 0.1 0402 C5019 1.09 4vWE Top 631 0.47 0603 C5111 1.09 4vWE Bottom 681 0.1 0402 C5030 1.11 4vWE Top 738 4.7 0805 C5037 1.11 4vWE Top 563 2.2 0603 C5018 1.14 4vWE Top 681 1 0603 C5021 1.17 4vWE Top 761 0.22 0603 C5026 1.18 4vWE Top 792 22 1206 C5079 1.32 4vWE Bottom 542 0.1 0402 C5080 1.58 4vWE Bottom 602 0.1 0402 |
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