DM504 datasheet(190/211 Pages) TI1

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190

DM504

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Applications, Implementation, and Layout

Via Technology: Through-hole

Copper Weight:

•

½ oz for all signal layers.

•

1-2oz for all power plane for improved PCB heat spreading.

7.3.7.2

vdd_dspeve Example Analysis

Maximum acceptable PCB resistance (Reff) between the PMIC and Processor input power balls should not

exceed 33mΩ per Table 7-3 and (7).

Maximum decoupling capacitance loop inductance (LL) between Processor input power balls and

decoupling capacitances should not exceed 2.5nH per Table 7-3 and (7) (ESL NOT included)

Impedance target for key frequency of interest between Processor input power balls and PMIC’s SMPS

output power balls should not exceed 54mΩ per Table 7-3 and (7).

Table 7-6. Example PCB vdd_dspeve PI Analysis Summary

Parameter

Recommendation

Example PCB

OPP

OPP_NOM

Clocking Rate

500 MHz

Voltage Level

1 V

Max Current Draw

1 A

Max Effective Resistance: Power

Inductor Segment Total Reff

13 mΩ

11.4mΩ

Max Loop Inductance

< 2.5 nH

0.73 - 1.58 nH

Impedance Target

54 mΩ for F < 20 MHz

28.8 mΩ for F < 20MHz

DM504 Datasheet(PDF) 190 Page - Texas Instruments

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