DM504 datasheet(188/211 Pages) TI1

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DM504

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Applications, Implementation, and Layout

Table 7-3. Recommended PDN and Decoupling Characteristics (1)(2)(3)(4)(5)

PDN Analysis:

Static

Dynamic

Number of Recommended Decoupling Capacitors per

Supply

Max Reff

(7)

[mΩ]

Dec. Cap.

Max LL(8) (6)

[nH]

Max

Impedance

[mΩ]

Frequency

range

of Interest

[MHz]

100

nF(6)

220

470

1μF

2.2 μF 4.7 μF

10 μF

22 μF

vdd_dspeve

2.5

≤20

vdd

≤50

vdds_ddr1,

vdds_ddr2,

vdds_ddr3

2.5

200

≤100

cap_vddram_cor

N/A

cap_vddram_cor

N/A

cap_vddram_dsp

eve

N/A

(1) For more information on peak-to-peak noise values, see the Recommended Operating Conditions table of the Electrical Characteristics

chapter.

(2) ESL must be as low as possible and must not exceed 0.5 nH.

(3) The PDN (Power Delivery Network) impedance characteristics are defined versus the device activity (that runs at different frequency)

based on the Recommended Operating Conditions table of the Electrical Characteristics chapter.

(4) The static drop requirement drives the maximum acceptable PCB resistance between the PMIC or the external SMPS and the processor

power balls.

(5) Assuming that the external SMPS (power IC) feedback sense is taken close to processor power balls.

(6) High-frequency (30 to 70MHz) PCB decoupling capacitors

(7) Maximum Total Reff from PMIC output to remote sensing feedback point located as close to the Device's point of load as possible.

(8) Maximum Loop Inductance for decoupling capacitor.

7.3.5

Power Supply Mapping

TPS65917 is a Power management IC (PMIC) that can be used for the Device design. TI is now

investigating an optimized solution for high power use cases so the TPS65917 is subject to change. An

alternate dual converter power solution using LP8732Q and LP8733Q are recommended. TI requires the

use of one of these PMIC solutions for the following reasons:

•

TI has validated its use with the Device

•

Board level margins including transient response and output accuracy are analyzed and optimized for

the entire system

•

Support for power sequencing requirements (refer to Section 5.9.3 Power Sequencing)

•

Support for Adaptive Voltage Scaling (AVS) Class 0 requirements, including TI provided software

It is possible that some voltage domains on the device are unused in some systems. In such cases, to

ensure device reliability, it is still required that the supply pins for the specific voltage domains are

connected to some core power supply output.

These unused supplies though can be combined with any of the core supplies that are used (active) in the

system. e.g. if IVA and GPU domains are not used, they can be combined with the CORE domain,

thereby having a single power supply driving the combined CORE, IVA and GPU domains.

For the combined rail, the following relaxations do apply:

•

The AVS voltage of active rail in the combined rail needs to be used to set the power supply

•

The decoupling capacitance should be set according to the active rail in the combined rail

Whenever we allow for combining of rails mapped on any of the SMPSes, the PDN guidelines that are the

most stringent of the rails combined should be implemented for the particular supply rail.

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