DM504 datasheet(196/211 Pages) TI1

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qspi1_sclk

QSPI device

clock input

QSPI deice

IOx, CS#

qspi1_d[x], qspi1_cs[y]

SPRS91v_PCB_QSPI_01

196

DM504

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Applications, Implementation, and Layout

•

Propagation delays and matching:

–

A to C = E to F

–

Matching skew: < 60Ps

–

A to B < 450pS

Figure 7-20. QSPI Interface High Level Schematic Mode 3 (POL=1, PHA=1)

NOTE

*0 Ω resistor (R1), located as close as possible to the qspi1_sclk pin, is placeholder for fine-

tuning if needed.

7.5

Differential Interfaces

7.5.1

General Routing Guidelines

To maximize signal integrity, proper routing techniques for differential signals are important for high-speed

designs. The following general routing guidelines describe the routing guidelines for differential lanes and

differential signals.

•

As much as possible, no other high-frequency signals must be routed in close proximity to the

differential pair.

•

Must be routed as differential traces on the same layer. The trace width and spacing must be chosen

to yield the differential impedance value recommended.

•

Minimize external components on differential lanes (like external ESD, probe points).

•

Through-hole pins are not recommended.

•

Differential lanes mustn’t cross image planes (ground planes).

•

No sharp bend on differential lanes.

DM504 Datasheet(PDF) 196 Page - Texas Instruments

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