DM504 datasheet(197/211 Pages) TI1

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DM504

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SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Applications, Implementation, and Layout

•

Number of vias on the differential pairs must be minimized, and identical on each line of the differential

pair. In case of multiple differential lanes in the same interface, all lines should have the same number

of vias.

•

Shielded routing is to be promoted as much as possible (for instance, signals must be routed on

internal layers that are inside power and/or ground planes).

7.5.2

CSI2 Board Design and Routing Guidelines

The MIPI D-PHY signals include the CSI2 camera serial interfaces to or from the Device.

For more information regarding the MIPI-PHY signals and corresponding balls, see Table 4-8, CSI2 Signal

Descriptions.

For more information, you can also see the MIPI D-PHY specification v1-01-00_r0-03 (specifically the

Interconnect and Lane Configuration and Annex B Interconnect Design Guidelines chapters).

In the next section, the PCB guidelines of the following differential interfaces are presented:

•

CSI2_0 MIPI CSI-2 at 1.5 Gbps

Table 7-9 lists the MIPI D-PHY interface signals in the Device.

Table 7-9. MIPI D-PHY Interface Signals in the Device

SIGNAL NAME

BALL

SIGNAL NAME

BALL

csi2_0_dx0

csi2_0_dy0

csi2_0_dx1

csi2_0_dy1

csi2_0_dx2

csi2_0_dy2

csi2_0_dx3

A10

csi2_0_dy3

B10

csi2_0_dx4

A11

csi2_0_dy4

B11

7.5.2.1

CSI2_0 MIPI CSI-2 (1.5 Gbps)

7.5.2.1.1 General Guidelines

The general guidelines for the PCB differential lines are:

•

Differential trace impedance Z0 = 100 Ω (minimum = 85 Ω, maximum = 115 Ω)

•

Total conductor length from the Device package pins to the peripheral device package pins is 25 to 30

cm with common FR4 PCB and flex materials.

NOTE

Longer interconnect length can be supported at the expense of detailed simulations of the

complete link including driver and receiver models.

The general rule of thumb for the space S = 2 × W is not designated (see Figure 7-18, Guard Illustration).

It is because although the S = 2 × W rule is a good rule of thumb, it is not always the best solution. The

electrical performance will be checked with the frequency-domain specification. Even though the designer

does not follow the S = 2 × W rule, the differential lines are ok if the lines satisfy the frequency-domain

specification.

Because the MIPI signals are used for low-power, single-ended signaling in addition to their high-speed

differential implementation, the pairs must be loosely coupled.

7.5.2.1.2 Length Mismatch Guidelines

7.5.2.1.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)

The guidelines of the length mismatch for CSI-2 are presented in Table 7-10.

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